1/* 2 * SPDX-License-Identifier: GPL-2.0 IBM-pibs 3 */ 4#include <config.h> 5#include <asm/ppc4xx.h> 6 7#include <ppc_asm.tmpl> 8#include <ppc_defs.h> 9 10#include <asm/cache.h> 11#include <asm/mmu.h> 12 13#define LI32(reg,val) \ 14 addis reg,0,val@h;\ 15 ori reg,reg,val@l 16 17#define WDCR_EBC(reg,val) \ 18 addi r4,0,reg;\ 19 mtdcr EBC0_CFGADDR,r4;\ 20 addis r4,0,val@h;\ 21 ori r4,r4,val@l;\ 22 mtdcr EBC0_CFGDATA,r4 23 24#define WDCR_SDRAM(reg,val) \ 25 addi r4,0,reg;\ 26 mtdcr SDRAM0_CFGADDR,r4;\ 27 addis r4,0,val@h;\ 28 ori r4,r4,val@l;\ 29 mtdcr SDRAM0_CFGDATA,r4 30 31/****************************************************************************** 32 * Function: ext_bus_cntlr_init 33 * 34 * Description: Configures EBC Controller and a few basic chip selects. 35 * 36 * CS0 is setup to get the Boot Flash out of the addresss range 37 * so that we may setup a stack. CS7 is setup so that we can 38 * access and reset the hardware watchdog. 39 * 40 * IMPORTANT: For pass1 this code must run from 41 * cache since you can not reliably change a peripheral banks 42 * timing register (pbxap) while running code from that bank. 43 * For ex., since we are running from ROM on bank 0, we can NOT 44 * execute the code that modifies bank 0 timings from ROM, so 45 * we run it from cache. 46 * 47 * Notes: Does NOT use the stack. 48 *****************************************************************************/ 49 .section ".text" 50 .align 2 51 .globl ext_bus_cntlr_init 52 .type ext_bus_cntlr_init, @function 53ext_bus_cntlr_init: 54 mflr r0 55 /******************************************************************** 56 * Prefetch entire ext_bus_cntrl_init function into the icache. 57 * This is necessary because we are going to change the same CS we 58 * are executing from. Otherwise a CPU lockup may occur. 59 *******************************************************************/ 60 bl ..getAddr 61..getAddr: 62 mflr r3 /* get address of ..getAddr */ 63 64 /* Calculate number of cache lines for this function */ 65 addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2) 66 mtctr r4 67..ebcloop: 68 icbt r0, r3 /* prefetch cache line for addr in r3*/ 69 addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */ 70 bdnz ..ebcloop /* continue for $CTR cache lines */ 71 72 /******************************************************************** 73 * Delay to ensure all accesses to ROM are complete before changing 74 * bank 0 timings. 200usec should be enough. 75 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles. 76 *******************************************************************/ 77 addis r3, 0, 0x0 78 ori r3, r3, 0xA000 /* wait 200us from reset */ 79 mtctr r3 80..spinlp: 81 bdnz ..spinlp /* spin loop */ 82 83 /******************************************************************** 84 * SETUP CPC0_CR0 85 *******************************************************************/ 86 LI32(r4, 0x00c01030) 87 mtdcr CPC0_CR0, r4 88 89 /******************************************************************** 90 * Setup CPC0_CR1: Change PCIINT signal to PerWE 91 *******************************************************************/ 92 mfdcr r4, CPC0_CR1 93 ori r4, r4, 0x4000 94 mtdcr CPC0_CR1, r4 95 96 /******************************************************************** 97 * Setup External Bus Controller (EBC). 98 *******************************************************************/ 99 WDCR_EBC(EBC0_CFG, 0xd84c0000) 100 /******************************************************************** 101 * Memory Bank 0 (Intel 28F640J3 Flash) initialization 102 *******************************************************************/ 103 /*WDCR_EBC(PB1AP, 0x03055200)*/ 104 /*WDCR_EBC(PB1AP, 0x04055200)*/ 105 WDCR_EBC(PB1AP, 0x08055200) 106 WDCR_EBC(PB0CR, 0xff87a000) 107 /******************************************************************** 108 * Memory Bank 3 (Xilinx XC95144 CPLD) initialization 109 *******************************************************************/ 110 /*WDCR_EBC(PB3AP, 0x07869200)*/ 111 WDCR_EBC(PB3AP, 0x04055200) 112 WDCR_EBC(PB3CR, 0xf081c000) 113 /******************************************************************** 114 * Memory Bank 1,2,4-7 (Unused) initialization 115 *******************************************************************/ 116 WDCR_EBC(PB1AP, 0) 117 WDCR_EBC(PB1CR, 0) 118 WDCR_EBC(PB2AP, 0) 119 WDCR_EBC(PB2CR, 0) 120 WDCR_EBC(PB4AP, 0) 121 WDCR_EBC(PB4CR, 0) 122 WDCR_EBC(PB5AP, 0) 123 WDCR_EBC(PB5CR, 0) 124 WDCR_EBC(PB6AP, 0) 125 WDCR_EBC(PB6CR, 0) 126 WDCR_EBC(PB7AP, 0) 127 WDCR_EBC(PB7CR, 0) 128 129 /* We are all done */ 130 mtlr r0 /* Restore link register */ 131 blr /* Return to calling function */ 132.Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init 133/* end ext_bus_cntlr_init() */ 134 135/****************************************************************************** 136 * Function: sdram_init 137 * 138 * Description: Configures SDRAM memory banks. 139 * 140 * Notes: Does NOT use the stack. 141 *****************************************************************************/ 142 .section ".text" 143 .align 2 144 .globl sdram_init 145 .type sdram_init, @function 146sdram_init: 147 148 /* 149 * Disable memory controller to allow 150 * values to be changed. 151 */ 152 WDCR_SDRAM(SDRAM0_CFG, 0x00000000) 153 154 /* 155 * Configure Memory Banks 156 */ 157 WDCR_SDRAM(SDRAM0_B0CR, 0x00062001) 158 WDCR_SDRAM(SDRAM0_B1CR, 0x00000000) 159 WDCR_SDRAM(SDRAM0_B2CR, 0x00000000) 160 WDCR_SDRAM(SDRAM0_B3CR, 0x00000000) 161 162 /* 163 * Set up SDTR1 (SDRAM Timing Register) 164 */ 165 WDCR_SDRAM(SDRAM0_TR, 0x00854009) 166 167 /* 168 * Set RTR (Refresh Timing Register) 169 */ 170 WDCR_SDRAM(SDRAM0_RTR, 0x10000000) 171 /* WDCR_SDRAM(SDRAM0_RTR, 0x05f00000) */ 172 173 /******************************************************************** 174 * Delay to ensure 200usec have elapsed since reset. Assume worst 175 * case that the core is running 200Mhz: 176 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles 177 *******************************************************************/ 178 addis r3, 0, 0x0000 179 ori r3, r3, 0xA000 /* Wait >200us from reset */ 180 mtctr r3 181..spinlp2: 182 bdnz ..spinlp2 /* spin loop */ 183 184 /******************************************************************** 185 * Set memory controller options reg, MCOPT1. 186 *******************************************************************/ 187 WDCR_SDRAM(SDRAM0_CFG,0x80800000) 188 189..sdri_done: 190 blr /* Return to calling function */ 191.Lfe1: .size sdram_init,.Lfe1-sdram_init 192/* end sdram_init() */ 193