LXR uboot/drivers/mmc/socfpga_dw

   1/*
   2 * (C) Copyright 2013 Altera Corporation <www.altera.com>
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#include <common.h>
   8#include <malloc.h>
   9#include <dwmmc.h>
  10#include <asm/arch/dwmmc.h>
  11#include <asm/arch/clock_manager.h>
  12#include <asm/arch/system_manager.h>
  13
  14static const struct socfpga_clock_manager *clock_manager_base =
  15                (void *)SOCFPGA_CLKMGR_ADDRESS;
  16static const struct socfpga_system_manager *system_manager_base =
  17                (void *)SOCFPGA_SYSMGR_ADDRESS;
  18
  19static char *SOCFPGA_NAME = "SOCFPGA DWMMC";
  20
  21static void socfpga_dwmci_clksel(struct dwmci_host *host)
  22{
  23        unsigned int drvsel;
  24        unsigned int smplsel;
  25
  26        /* Disable SDMMC clock. */
  27        clrbits_le32(&clock_manager_base->per_pll_en,
  28                CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
  29
  30        /* Configures drv_sel and smpl_sel */
  31        drvsel = CONFIG_SOCFPGA_DWMMC_DRVSEL;
  32        smplsel = CONFIG_SOCFPGA_DWMMC_SMPSEL;
  33
  34        debug("%s: drvsel %d smplsel %d\n", __func__, drvsel, smplsel);
  35        writel(SYSMGR_SDMMC_CTRL_SET(smplsel, drvsel),
  36                &system_manager_base->sdmmcgrp_ctrl);
  37
  38        debug("%s: SYSMGR_SDMMCGRP_CTRL_REG = 0x%x\n", __func__,
  39                readl(&system_manager_base->sdmmcgrp_ctrl));
  40
  41        /* Enable SDMMC clock */
  42        setbits_le32(&clock_manager_base->per_pll_en,
  43                CLKMGR_PERPLLGRP_EN_SDMMCCLK_MASK);
  44}
  45
  46int socfpga_dwmmc_init(u32 regbase, int bus_width, int index)
  47{
  48        struct dwmci_host *host = NULL;
  49        host = calloc(sizeof(struct dwmci_host), 1);
  50        if (!host) {
  51                printf("dwmci_host calloc fail!\n");
  52                return -1;
  53        }
  54
  55        host->name = SOCFPGA_NAME;
  56        host->ioaddr = (void *)regbase;
  57        host->buswidth = bus_width;
  58        host->clksel = socfpga_dwmci_clksel;
  59        host->dev_index = index;
  60        /* fixed clock divide by 4 which due to the SDMMC wrapper */
  61        host->bus_hz = CONFIG_SOCFPGA_DWMMC_BUS_HZ;
  62        host->fifoth_val = MSIZE(0x2) |
  63                RX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2 - 1) |
  64                TX_WMARK(CONFIG_SOCFPGA_DWMMC_FIFO_DEPTH / 2);
  65
  66        return add_dwmci(host, host->bus_hz, 400000);
  67}
  68
  69