1
2
3
4
5
6
7
8#include <asm/unaligned.h>
9#include <common.h>
10#include <usb.h>
11#include <linux/mii.h>
12#include "usb_ether.h"
13#include <malloc.h>
14
15
16
17
18#define LED_GPIO_CFG (0x24)
19#define LED_GPIO_CFG_SPD_LED (0x01000000)
20#define LED_GPIO_CFG_LNK_LED (0x00100000)
21#define LED_GPIO_CFG_FDX_LED (0x00010000)
22
23
24#define TX_CMD_A_FIRST_SEG_ 0x00002000
25#define TX_CMD_A_LAST_SEG_ 0x00001000
26
27
28#define RX_STS_FL_ 0x3FFF0000
29#define RX_STS_ES_ 0x00008000
30
31
32#define ID_REV 0x00
33
34#define INT_STS 0x08
35
36#define TX_CFG 0x10
37#define TX_CFG_ON_ 0x00000004
38
39#define HW_CFG 0x14
40#define HW_CFG_BIR_ 0x00001000
41#define HW_CFG_RXDOFF_ 0x00000600
42#define HW_CFG_MEF_ 0x00000020
43#define HW_CFG_BCE_ 0x00000002
44#define HW_CFG_LRST_ 0x00000008
45
46#define PM_CTRL 0x20
47#define PM_CTL_PHY_RST_ 0x00000010
48
49#define AFC_CFG 0x2C
50
51
52
53
54
55
56
57#define AFC_CFG_DEFAULT 0x00F830A1
58
59#define E2P_CMD 0x30
60#define E2P_CMD_BUSY_ 0x80000000
61#define E2P_CMD_READ_ 0x00000000
62#define E2P_CMD_TIMEOUT_ 0x00000400
63#define E2P_CMD_LOADED_ 0x00000200
64#define E2P_CMD_ADDR_ 0x000001FF
65
66#define E2P_DATA 0x34
67
68#define BURST_CAP 0x38
69
70#define INT_EP_CTL 0x68
71#define INT_EP_CTL_PHY_INT_ 0x00008000
72
73#define BULK_IN_DLY 0x6C
74
75
76#define MAC_CR 0x100
77#define MAC_CR_MCPAS_ 0x00080000
78#define MAC_CR_PRMS_ 0x00040000
79#define MAC_CR_HPFILT_ 0x00002000
80#define MAC_CR_TXEN_ 0x00000008
81#define MAC_CR_RXEN_ 0x00000004
82
83#define ADDRH 0x104
84
85#define ADDRL 0x108
86
87#define MII_ADDR 0x114
88#define MII_WRITE_ 0x02
89#define MII_BUSY_ 0x01
90#define MII_READ_ 0x00
91
92#define MII_DATA 0x118
93
94#define FLOW 0x11C
95
96#define VLAN1 0x120
97
98#define COE_CR 0x130
99#define Tx_COE_EN_ 0x00010000
100#define Rx_COE_EN_ 0x00000001
101
102
103#define PHY_INT_SRC 29
104
105#define PHY_INT_MASK 30
106#define PHY_INT_MASK_ANEG_COMP_ ((u16)0x0040)
107#define PHY_INT_MASK_LINK_DOWN_ ((u16)0x0010)
108#define PHY_INT_MASK_DEFAULT_ (PHY_INT_MASK_ANEG_COMP_ | \
109 PHY_INT_MASK_LINK_DOWN_)
110
111
112#define USB_VENDOR_REQUEST_WRITE_REGISTER 0xA0
113#define USB_VENDOR_REQUEST_READ_REGISTER 0xA1
114
115
116#define HS_USB_PKT_SIZE 512
117#define FS_USB_PKT_SIZE 64
118#define DEFAULT_HS_BURST_CAP_SIZE (16 * 1024 + 5 * HS_USB_PKT_SIZE)
119#define DEFAULT_FS_BURST_CAP_SIZE (6 * 1024 + 33 * FS_USB_PKT_SIZE)
120#define DEFAULT_BULK_IN_DELAY 0x00002000
121#define MAX_SINGLE_PACKET_SIZE 2048
122#define EEPROM_MAC_OFFSET 0x01
123#define SMSC95XX_INTERNAL_PHY_ID 1
124#define ETH_P_8021Q 0x8100
125
126
127#define SMSC95XX_BASE_NAME "sms"
128#define USB_CTRL_SET_TIMEOUT 5000
129#define USB_CTRL_GET_TIMEOUT 5000
130#define USB_BULK_SEND_TIMEOUT 5000
131#define USB_BULK_RECV_TIMEOUT 5000
132
133#define AX_RX_URB_SIZE 2048
134#define PHY_CONNECT_TIMEOUT 5000
135
136#define TURBO_MODE
137
138
139static int curr_eth_dev;
140
141
142struct smsc95xx_private {
143 size_t rx_urb_size;
144 u32 mac_cr;
145 int have_hwaddr;
146};
147
148
149
150
151static int smsc95xx_write_reg(struct ueth_data *dev, u32 index, u32 data)
152{
153 int len;
154 ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1);
155
156 cpu_to_le32s(&data);
157 tmpbuf[0] = data;
158
159 len = usb_control_msg(dev->pusb_dev, usb_sndctrlpipe(dev->pusb_dev, 0),
160 USB_VENDOR_REQUEST_WRITE_REGISTER,
161 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
162 00, index, tmpbuf, sizeof(data), USB_CTRL_SET_TIMEOUT);
163 if (len != sizeof(data)) {
164 debug("smsc95xx_write_reg failed: index=%d, data=%d, len=%d",
165 index, data, len);
166 return -1;
167 }
168 return 0;
169}
170
171static int smsc95xx_read_reg(struct ueth_data *dev, u32 index, u32 *data)
172{
173 int len;
174 ALLOC_CACHE_ALIGN_BUFFER(u32, tmpbuf, 1);
175
176 len = usb_control_msg(dev->pusb_dev, usb_rcvctrlpipe(dev->pusb_dev, 0),
177 USB_VENDOR_REQUEST_READ_REGISTER,
178 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
179 00, index, tmpbuf, sizeof(data), USB_CTRL_GET_TIMEOUT);
180 *data = tmpbuf[0];
181 if (len != sizeof(data)) {
182 debug("smsc95xx_read_reg failed: index=%d, len=%d",
183 index, len);
184 return -1;
185 }
186
187 le32_to_cpus(data);
188 return 0;
189}
190
191
192static int smsc95xx_phy_wait_not_busy(struct ueth_data *dev)
193{
194 unsigned long start_time = get_timer(0);
195 u32 val;
196
197 do {
198 smsc95xx_read_reg(dev, MII_ADDR, &val);
199 if (!(val & MII_BUSY_))
200 return 0;
201 } while (get_timer(start_time) < 1 * 1000 * 1000);
202
203 return -1;
204}
205
206static int smsc95xx_mdio_read(struct ueth_data *dev, int phy_id, int idx)
207{
208 u32 val, addr;
209
210
211 if (smsc95xx_phy_wait_not_busy(dev)) {
212 debug("MII is busy in smsc95xx_mdio_read\n");
213 return -1;
214 }
215
216
217 addr = (phy_id << 11) | (idx << 6) | MII_READ_;
218 smsc95xx_write_reg(dev, MII_ADDR, addr);
219
220 if (smsc95xx_phy_wait_not_busy(dev)) {
221 debug("Timed out reading MII reg %02X\n", idx);
222 return -1;
223 }
224
225 smsc95xx_read_reg(dev, MII_DATA, &val);
226
227 return (u16)(val & 0xFFFF);
228}
229
230static void smsc95xx_mdio_write(struct ueth_data *dev, int phy_id, int idx,
231 int regval)
232{
233 u32 val, addr;
234
235
236 if (smsc95xx_phy_wait_not_busy(dev)) {
237 debug("MII is busy in smsc95xx_mdio_write\n");
238 return;
239 }
240
241 val = regval;
242 smsc95xx_write_reg(dev, MII_DATA, val);
243
244
245 addr = (phy_id << 11) | (idx << 6) | MII_WRITE_;
246 smsc95xx_write_reg(dev, MII_ADDR, addr);
247
248 if (smsc95xx_phy_wait_not_busy(dev))
249 debug("Timed out writing MII reg %02X\n", idx);
250}
251
252static int smsc95xx_eeprom_confirm_not_busy(struct ueth_data *dev)
253{
254 unsigned long start_time = get_timer(0);
255 u32 val;
256
257 do {
258 smsc95xx_read_reg(dev, E2P_CMD, &val);
259 if (!(val & E2P_CMD_BUSY_))
260 return 0;
261 udelay(40);
262 } while (get_timer(start_time) < 1 * 1000 * 1000);
263
264 debug("EEPROM is busy\n");
265 return -1;
266}
267
268static int smsc95xx_wait_eeprom(struct ueth_data *dev)
269{
270 unsigned long start_time = get_timer(0);
271 u32 val;
272
273 do {
274 smsc95xx_read_reg(dev, E2P_CMD, &val);
275 if (!(val & E2P_CMD_BUSY_) || (val & E2P_CMD_TIMEOUT_))
276 break;
277 udelay(40);
278 } while (get_timer(start_time) < 1 * 1000 * 1000);
279
280 if (val & (E2P_CMD_TIMEOUT_ | E2P_CMD_BUSY_)) {
281 debug("EEPROM read operation timeout\n");
282 return -1;
283 }
284 return 0;
285}
286
287static int smsc95xx_read_eeprom(struct ueth_data *dev, u32 offset, u32 length,
288 u8 *data)
289{
290 u32 val;
291 int i, ret;
292
293 ret = smsc95xx_eeprom_confirm_not_busy(dev);
294 if (ret)
295 return ret;
296
297 for (i = 0; i < length; i++) {
298 val = E2P_CMD_BUSY_ | E2P_CMD_READ_ | (offset & E2P_CMD_ADDR_);
299 smsc95xx_write_reg(dev, E2P_CMD, val);
300
301 ret = smsc95xx_wait_eeprom(dev);
302 if (ret < 0)
303 return ret;
304
305 smsc95xx_read_reg(dev, E2P_DATA, &val);
306 data[i] = val & 0xFF;
307 offset++;
308 }
309 return 0;
310}
311
312
313
314
315
316
317static int mii_nway_restart(struct ueth_data *dev)
318{
319 int bmcr;
320 int r = -1;
321
322
323 bmcr = smsc95xx_mdio_read(dev, dev->phy_id, MII_BMCR);
324
325 if (bmcr & BMCR_ANENABLE) {
326 bmcr |= BMCR_ANRESTART;
327 smsc95xx_mdio_write(dev, dev->phy_id, MII_BMCR, bmcr);
328 r = 0;
329 }
330 return r;
331}
332
333static int smsc95xx_phy_initialize(struct ueth_data *dev)
334{
335 smsc95xx_mdio_write(dev, dev->phy_id, MII_BMCR, BMCR_RESET);
336 smsc95xx_mdio_write(dev, dev->phy_id, MII_ADVERTISE,
337 ADVERTISE_ALL | ADVERTISE_CSMA | ADVERTISE_PAUSE_CAP |
338 ADVERTISE_PAUSE_ASYM);
339
340
341 smsc95xx_mdio_read(dev, dev->phy_id, PHY_INT_SRC);
342
343 smsc95xx_mdio_write(dev, dev->phy_id, PHY_INT_MASK,
344 PHY_INT_MASK_DEFAULT_);
345 mii_nway_restart(dev);
346
347 debug("phy initialised succesfully\n");
348 return 0;
349}
350
351static int smsc95xx_init_mac_address(struct eth_device *eth,
352 struct ueth_data *dev)
353{
354
355 if (smsc95xx_read_eeprom(dev, EEPROM_MAC_OFFSET, ETH_ALEN,
356 eth->enetaddr) == 0) {
357 if (is_valid_ether_addr(eth->enetaddr)) {
358
359 debug("MAC address read from EEPROM\n");
360 return 0;
361 }
362 }
363
364
365
366
367
368 return -1;
369}
370
371static int smsc95xx_write_hwaddr(struct eth_device *eth)
372{
373 struct ueth_data *dev = (struct ueth_data *)eth->priv;
374 struct smsc95xx_private *priv = dev->dev_priv;
375 u32 addr_lo = __get_unaligned_le32(ð->enetaddr[0]);
376 u32 addr_hi = __get_unaligned_le16(ð->enetaddr[4]);
377 int ret;
378
379
380 debug("** %s()\n", __func__);
381 ret = smsc95xx_write_reg(dev, ADDRL, addr_lo);
382 if (ret < 0)
383 return ret;
384
385 ret = smsc95xx_write_reg(dev, ADDRH, addr_hi);
386 if (ret < 0)
387 return ret;
388
389 debug("MAC %pM\n", eth->enetaddr);
390 priv->have_hwaddr = 1;
391 return 0;
392}
393
394
395static int smsc95xx_set_csums(struct ueth_data *dev,
396 int use_tx_csum, int use_rx_csum)
397{
398 u32 read_buf;
399 int ret = smsc95xx_read_reg(dev, COE_CR, &read_buf);
400 if (ret < 0)
401 return ret;
402
403 if (use_tx_csum)
404 read_buf |= Tx_COE_EN_;
405 else
406 read_buf &= ~Tx_COE_EN_;
407
408 if (use_rx_csum)
409 read_buf |= Rx_COE_EN_;
410 else
411 read_buf &= ~Rx_COE_EN_;
412
413 ret = smsc95xx_write_reg(dev, COE_CR, read_buf);
414 if (ret < 0)
415 return ret;
416
417 debug("COE_CR = 0x%08x\n", read_buf);
418 return 0;
419}
420
421static void smsc95xx_set_multicast(struct ueth_data *dev)
422{
423 struct smsc95xx_private *priv = dev->dev_priv;
424
425
426 priv->mac_cr &= ~(MAC_CR_PRMS_ | MAC_CR_MCPAS_ | MAC_CR_HPFILT_);
427}
428
429
430static void smsc95xx_start_tx_path(struct ueth_data *dev)
431{
432 struct smsc95xx_private *priv = dev->dev_priv;
433 u32 reg_val;
434
435
436 priv->mac_cr |= MAC_CR_TXEN_;
437
438 smsc95xx_write_reg(dev, MAC_CR, priv->mac_cr);
439
440
441 reg_val = TX_CFG_ON_;
442 smsc95xx_write_reg(dev, TX_CFG, reg_val);
443}
444
445
446static void smsc95xx_start_rx_path(struct ueth_data *dev)
447{
448 struct smsc95xx_private *priv = dev->dev_priv;
449
450 priv->mac_cr |= MAC_CR_RXEN_;
451 smsc95xx_write_reg(dev, MAC_CR, priv->mac_cr);
452}
453
454
455
456
457static int smsc95xx_init(struct eth_device *eth, bd_t *bd)
458{
459 int ret;
460 u32 write_buf;
461 u32 read_buf;
462 u32 burst_cap;
463 int timeout;
464 struct ueth_data *dev = (struct ueth_data *)eth->priv;
465 struct smsc95xx_private *priv =
466 (struct smsc95xx_private *)dev->dev_priv;
467#define TIMEOUT_RESOLUTION 50
468 int link_detected;
469
470 debug("** %s()\n", __func__);
471 dev->phy_id = SMSC95XX_INTERNAL_PHY_ID;
472
473 write_buf = HW_CFG_LRST_;
474 ret = smsc95xx_write_reg(dev, HW_CFG, write_buf);
475 if (ret < 0)
476 return ret;
477
478 timeout = 0;
479 do {
480 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
481 if (ret < 0)
482 return ret;
483 udelay(10 * 1000);
484 timeout++;
485 } while ((read_buf & HW_CFG_LRST_) && (timeout < 100));
486
487 if (timeout >= 100) {
488 debug("timeout waiting for completion of Lite Reset\n");
489 return -1;
490 }
491
492 write_buf = PM_CTL_PHY_RST_;
493 ret = smsc95xx_write_reg(dev, PM_CTRL, write_buf);
494 if (ret < 0)
495 return ret;
496
497 timeout = 0;
498 do {
499 ret = smsc95xx_read_reg(dev, PM_CTRL, &read_buf);
500 if (ret < 0)
501 return ret;
502 udelay(10 * 1000);
503 timeout++;
504 } while ((read_buf & PM_CTL_PHY_RST_) && (timeout < 100));
505 if (timeout >= 100) {
506 debug("timeout waiting for PHY Reset\n");
507 return -1;
508 }
509 if (!priv->have_hwaddr && smsc95xx_init_mac_address(eth, dev) == 0)
510 priv->have_hwaddr = 1;
511 if (!priv->have_hwaddr) {
512 puts("Error: SMSC95xx: No MAC address set - set usbethaddr\n");
513 return -1;
514 }
515 if (smsc95xx_write_hwaddr(eth) < 0)
516 return -1;
517
518 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
519 if (ret < 0)
520 return ret;
521 debug("Read Value from HW_CFG : 0x%08x\n", read_buf);
522
523 read_buf |= HW_CFG_BIR_;
524 ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
525 if (ret < 0)
526 return ret;
527
528 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
529 if (ret < 0)
530 return ret;
531 debug("Read Value from HW_CFG after writing "
532 "HW_CFG_BIR_: 0x%08x\n", read_buf);
533
534#ifdef TURBO_MODE
535 if (dev->pusb_dev->speed == USB_SPEED_HIGH) {
536 burst_cap = DEFAULT_HS_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
537 priv->rx_urb_size = DEFAULT_HS_BURST_CAP_SIZE;
538 } else {
539 burst_cap = DEFAULT_FS_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
540 priv->rx_urb_size = DEFAULT_FS_BURST_CAP_SIZE;
541 }
542#else
543 burst_cap = 0;
544 priv->rx_urb_size = MAX_SINGLE_PACKET_SIZE;
545#endif
546 debug("rx_urb_size=%ld\n", (ulong)priv->rx_urb_size);
547
548 ret = smsc95xx_write_reg(dev, BURST_CAP, burst_cap);
549 if (ret < 0)
550 return ret;
551
552 ret = smsc95xx_read_reg(dev, BURST_CAP, &read_buf);
553 if (ret < 0)
554 return ret;
555 debug("Read Value from BURST_CAP after writing: 0x%08x\n", read_buf);
556
557 read_buf = DEFAULT_BULK_IN_DELAY;
558 ret = smsc95xx_write_reg(dev, BULK_IN_DLY, read_buf);
559 if (ret < 0)
560 return ret;
561
562 ret = smsc95xx_read_reg(dev, BULK_IN_DLY, &read_buf);
563 if (ret < 0)
564 return ret;
565 debug("Read Value from BULK_IN_DLY after writing: "
566 "0x%08x\n", read_buf);
567
568 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
569 if (ret < 0)
570 return ret;
571 debug("Read Value from HW_CFG: 0x%08x\n", read_buf);
572
573#ifdef TURBO_MODE
574 read_buf |= (HW_CFG_MEF_ | HW_CFG_BCE_);
575#endif
576 read_buf &= ~HW_CFG_RXDOFF_;
577
578#define NET_IP_ALIGN 0
579 read_buf |= NET_IP_ALIGN << 9;
580
581 ret = smsc95xx_write_reg(dev, HW_CFG, read_buf);
582 if (ret < 0)
583 return ret;
584
585 ret = smsc95xx_read_reg(dev, HW_CFG, &read_buf);
586 if (ret < 0)
587 return ret;
588 debug("Read Value from HW_CFG after writing: 0x%08x\n", read_buf);
589
590 write_buf = 0xFFFFFFFF;
591 ret = smsc95xx_write_reg(dev, INT_STS, write_buf);
592 if (ret < 0)
593 return ret;
594
595 ret = smsc95xx_read_reg(dev, ID_REV, &read_buf);
596 if (ret < 0)
597 return ret;
598 debug("ID_REV = 0x%08x\n", read_buf);
599
600
601 write_buf = LED_GPIO_CFG_SPD_LED | LED_GPIO_CFG_LNK_LED |
602 LED_GPIO_CFG_FDX_LED;
603 ret = smsc95xx_write_reg(dev, LED_GPIO_CFG, write_buf);
604 if (ret < 0)
605 return ret;
606 debug("LED_GPIO_CFG set\n");
607
608
609 write_buf = 0;
610 ret = smsc95xx_write_reg(dev, FLOW, write_buf);
611 if (ret < 0)
612 return ret;
613
614 read_buf = AFC_CFG_DEFAULT;
615 ret = smsc95xx_write_reg(dev, AFC_CFG, read_buf);
616 if (ret < 0)
617 return ret;
618
619 ret = smsc95xx_read_reg(dev, MAC_CR, &priv->mac_cr);
620 if (ret < 0)
621 return ret;
622
623
624 write_buf = (u32)ETH_P_8021Q;
625 ret = smsc95xx_write_reg(dev, VLAN1, write_buf);
626 if (ret < 0)
627 return ret;
628
629
630 ret = smsc95xx_set_csums(dev, 0, 0);
631 if (ret < 0) {
632 debug("Failed to set csum offload: %d\n", ret);
633 return ret;
634 }
635 smsc95xx_set_multicast(dev);
636
637 if (smsc95xx_phy_initialize(dev) < 0)
638 return -1;
639 ret = smsc95xx_read_reg(dev, INT_EP_CTL, &read_buf);
640 if (ret < 0)
641 return ret;
642
643
644 read_buf |= INT_EP_CTL_PHY_INT_;
645
646 ret = smsc95xx_write_reg(dev, INT_EP_CTL, read_buf);
647 if (ret < 0)
648 return ret;
649
650 smsc95xx_start_tx_path(dev);
651 smsc95xx_start_rx_path(dev);
652
653 timeout = 0;
654 do {
655 link_detected = smsc95xx_mdio_read(dev, dev->phy_id, MII_BMSR)
656 & BMSR_LSTATUS;
657 if (!link_detected) {
658 if (timeout == 0)
659 printf("Waiting for Ethernet connection... ");
660 udelay(TIMEOUT_RESOLUTION * 1000);
661 timeout += TIMEOUT_RESOLUTION;
662 }
663 } while (!link_detected && timeout < PHY_CONNECT_TIMEOUT);
664 if (link_detected) {
665 if (timeout != 0)
666 printf("done.\n");
667 } else {
668 printf("unable to connect.\n");
669 return -1;
670 }
671 return 0;
672}
673
674static int smsc95xx_send(struct eth_device *eth, void* packet, int length)
675{
676 struct ueth_data *dev = (struct ueth_data *)eth->priv;
677 int err;
678 int actual_len;
679 u32 tx_cmd_a;
680 u32 tx_cmd_b;
681 ALLOC_CACHE_ALIGN_BUFFER(unsigned char, msg,
682 PKTSIZE + sizeof(tx_cmd_a) + sizeof(tx_cmd_b));
683
684 debug("** %s(), len %d, buf %#x\n", __func__, length, (int)msg);
685 if (length > PKTSIZE)
686 return -1;
687
688 tx_cmd_a = (u32)length | TX_CMD_A_FIRST_SEG_ | TX_CMD_A_LAST_SEG_;
689 tx_cmd_b = (u32)length;
690 cpu_to_le32s(&tx_cmd_a);
691 cpu_to_le32s(&tx_cmd_b);
692
693
694 memcpy(msg, &tx_cmd_a, sizeof(tx_cmd_a));
695 memcpy(msg + sizeof(tx_cmd_a), &tx_cmd_b, sizeof(tx_cmd_b));
696 memcpy(msg + sizeof(tx_cmd_a) + sizeof(tx_cmd_b), (void *)packet,
697 length);
698 err = usb_bulk_msg(dev->pusb_dev,
699 usb_sndbulkpipe(dev->pusb_dev, dev->ep_out),
700 (void *)msg,
701 length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b),
702 &actual_len,
703 USB_BULK_SEND_TIMEOUT);
704 debug("Tx: len = %u, actual = %u, err = %d\n",
705 length + sizeof(tx_cmd_a) + sizeof(tx_cmd_b),
706 actual_len, err);
707 return err;
708}
709
710static int smsc95xx_recv(struct eth_device *eth)
711{
712 struct ueth_data *dev = (struct ueth_data *)eth->priv;
713 DEFINE_CACHE_ALIGN_BUFFER(unsigned char, recv_buf, AX_RX_URB_SIZE);
714 unsigned char *buf_ptr;
715 int err;
716 int actual_len;
717 u32 packet_len;
718 int cur_buf_align;
719
720 debug("** %s()\n", __func__);
721 err = usb_bulk_msg(dev->pusb_dev,
722 usb_rcvbulkpipe(dev->pusb_dev, dev->ep_in),
723 (void *)recv_buf,
724 AX_RX_URB_SIZE,
725 &actual_len,
726 USB_BULK_RECV_TIMEOUT);
727 debug("Rx: len = %u, actual = %u, err = %d\n", AX_RX_URB_SIZE,
728 actual_len, err);
729 if (err != 0) {
730 debug("Rx: failed to receive\n");
731 return -1;
732 }
733 if (actual_len > AX_RX_URB_SIZE) {
734 debug("Rx: received too many bytes %d\n", actual_len);
735 return -1;
736 }
737
738 buf_ptr = recv_buf;
739 while (actual_len > 0) {
740
741
742
743
744 if (actual_len < sizeof(packet_len)) {
745 debug("Rx: incomplete packet length\n");
746 return -1;
747 }
748 memcpy(&packet_len, buf_ptr, sizeof(packet_len));
749 le32_to_cpus(&packet_len);
750 if (packet_len & RX_STS_ES_) {
751 debug("Rx: Error header=%#x", packet_len);
752 return -1;
753 }
754 packet_len = ((packet_len & RX_STS_FL_) >> 16);
755
756 if (packet_len > actual_len - sizeof(packet_len)) {
757 debug("Rx: too large packet: %d\n", packet_len);
758 return -1;
759 }
760
761
762 NetReceive(buf_ptr + sizeof(packet_len), packet_len - 4);
763
764
765 actual_len -= sizeof(packet_len) + packet_len;
766 buf_ptr += sizeof(packet_len) + packet_len;
767 cur_buf_align = (int)buf_ptr - (int)recv_buf;
768
769 if (cur_buf_align & 0x03) {
770 int align = 4 - (cur_buf_align & 0x03);
771
772 actual_len -= align;
773 buf_ptr += align;
774 }
775 }
776 return err;
777}
778
779static void smsc95xx_halt(struct eth_device *eth)
780{
781 debug("** %s()\n", __func__);
782}
783
784
785
786
787void smsc95xx_eth_before_probe(void)
788{
789 curr_eth_dev = 0;
790}
791
792struct smsc95xx_dongle {
793 unsigned short vendor;
794 unsigned short product;
795};
796
797static const struct smsc95xx_dongle smsc95xx_dongles[] = {
798 { 0x0424, 0xec00 },
799 { 0x0424, 0x9500 },
800 { 0x0424, 0x9730 },
801 { 0x0424, 0x9900 },
802 { 0x0424, 0x9e00 },
803 { 0x0000, 0x0000 }
804};
805
806
807int smsc95xx_eth_probe(struct usb_device *dev, unsigned int ifnum,
808 struct ueth_data *ss)
809{
810 struct usb_interface *iface;
811 struct usb_interface_descriptor *iface_desc;
812 int i;
813
814
815 iface = &dev->config.if_desc[ifnum];
816 iface_desc = &dev->config.if_desc[ifnum].desc;
817
818 for (i = 0; smsc95xx_dongles[i].vendor != 0; i++) {
819 if (dev->descriptor.idVendor == smsc95xx_dongles[i].vendor &&
820 dev->descriptor.idProduct == smsc95xx_dongles[i].product)
821
822 break;
823 }
824 if (smsc95xx_dongles[i].vendor == 0)
825 return 0;
826
827
828 debug("\n\nUSB Ethernet device detected\n");
829 memset(ss, '\0', sizeof(struct ueth_data));
830
831
832 ss->ifnum = ifnum;
833 ss->pusb_dev = dev;
834 ss->subclass = iface_desc->bInterfaceSubClass;
835 ss->protocol = iface_desc->bInterfaceProtocol;
836
837
838
839
840
841 for (i = 0; i < iface_desc->bNumEndpoints; i++) {
842
843 if ((iface->ep_desc[i].bmAttributes &
844 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_BULK) {
845 if (iface->ep_desc[i].bEndpointAddress & USB_DIR_IN)
846 ss->ep_in =
847 iface->ep_desc[i].bEndpointAddress &
848 USB_ENDPOINT_NUMBER_MASK;
849 else
850 ss->ep_out =
851 iface->ep_desc[i].bEndpointAddress &
852 USB_ENDPOINT_NUMBER_MASK;
853 }
854
855
856 if ((iface->ep_desc[i].bmAttributes &
857 USB_ENDPOINT_XFERTYPE_MASK) == USB_ENDPOINT_XFER_INT) {
858 ss->ep_int = iface->ep_desc[i].bEndpointAddress &
859 USB_ENDPOINT_NUMBER_MASK;
860 ss->irqinterval = iface->ep_desc[i].bInterval;
861 }
862 }
863 debug("Endpoints In %d Out %d Int %d\n",
864 ss->ep_in, ss->ep_out, ss->ep_int);
865
866
867 if (usb_set_interface(dev, iface_desc->bInterfaceNumber, 0) ||
868 !ss->ep_in || !ss->ep_out || !ss->ep_int) {
869 debug("Problems with device\n");
870 return 0;
871 }
872 dev->privptr = (void *)ss;
873
874
875 ss->dev_priv = calloc(1, sizeof(struct smsc95xx_private));
876 if (!ss->dev_priv)
877 return 0;
878
879 return 1;
880}
881
882int smsc95xx_eth_get_info(struct usb_device *dev, struct ueth_data *ss,
883 struct eth_device *eth)
884{
885 debug("** %s()\n", __func__);
886 if (!eth) {
887 debug("%s: missing parameter.\n", __func__);
888 return 0;
889 }
890 sprintf(eth->name, "%s%d", SMSC95XX_BASE_NAME, curr_eth_dev++);
891 eth->init = smsc95xx_init;
892 eth->send = smsc95xx_send;
893 eth->recv = smsc95xx_recv;
894 eth->halt = smsc95xx_halt;
895 eth->write_hwaddr = smsc95xx_write_hwaddr;
896 eth->priv = ss;
897 return 1;
898}
899
