LXR uboot/drivers/usb/host/xhci-exynos5.c

   1/*
   2 * SAMSUNG EXYNOS5 USB HOST XHCI Controller
   3 *
   4 * Copyright (C) 2012 Samsung Electronics Co.Ltd
   5 *      Vivek Gautam <gautam.vivek@samsung.com>
   6 *      Vikas Sajjan <vikas.sajjan@samsung.com>
   7 *
   8 * SPDX-License-Identifier:     GPL-2.0+
   9 */
  10
  11/*
  12 * This file is a conglomeration for DWC3-init sequence and further
  13 * exynos5 specific PHY-init sequence.
  14 */
  15
  16#include <common.h>
  17#include <fdtdec.h>
  18#include <libfdt.h>
  19#include <malloc.h>
  20#include <usb.h>
  21#include <watchdog.h>
  22#include <asm/arch/cpu.h>
  23#include <asm/arch/power.h>
  24#include <asm/arch/xhci-exynos.h>
  25#include <asm/gpio.h>
  26#include <asm-generic/errno.h>
  27#include <linux/compat.h>
  28#include <linux/usb/dwc3.h>
  29
  30#include "xhci.h"
  31
  32/* Declare global data pointer */
  33DECLARE_GLOBAL_DATA_PTR;
  34
  35/**
  36 * Contains pointers to register base addresses
  37 * for the usb controller.
  38 */
  39struct exynos_xhci {
  40        struct exynos_usb3_phy *usb3_phy;
  41        struct xhci_hccr *hcd;
  42        struct dwc3 *dwc3_reg;
  43        struct fdt_gpio_state vbus_gpio;
  44};
  45
  46static struct exynos_xhci exynos;
  47
  48#ifdef CONFIG_OF_CONTROL
  49static int exynos_usb3_parse_dt(const void *blob, struct exynos_xhci *exynos)
  50{
  51        fdt_addr_t addr;
  52        unsigned int node;
  53        int depth;
  54
  55        node = fdtdec_next_compatible(blob, 0, COMPAT_SAMSUNG_EXYNOS5_XHCI);
  56        if (node <= 0) {
  57                debug("XHCI: Can't get device node for xhci\n");
  58                return -ENODEV;
  59        }
  60
  61        /*
  62         * Get the base address for XHCI controller from the device node
  63         */
  64        addr = fdtdec_get_addr(blob, node, "reg");
  65        if (addr == FDT_ADDR_T_NONE) {
  66                debug("Can't get the XHCI register base address\n");
  67                return -ENXIO;
  68        }
  69        exynos->hcd = (struct xhci_hccr *)addr;
  70
  71        /* Vbus gpio */
  72        fdtdec_decode_gpio(blob, node, "samsung,vbus-gpio", &exynos->vbus_gpio);
  73
  74        depth = 0;
  75        node = fdtdec_next_compatible_subnode(blob, node,
  76                                COMPAT_SAMSUNG_EXYNOS5_USB3_PHY, &depth);
  77        if (node <= 0) {
  78                debug("XHCI: Can't get device node for usb3-phy controller\n");
  79                return -ENODEV;
  80        }
  81
  82        /*
  83         * Get the base address for usbphy from the device node
  84         */
  85        exynos->usb3_phy = (struct exynos_usb3_phy *)fdtdec_get_addr(blob, node,
  86                                                                "reg");
  87        if (exynos->usb3_phy == NULL) {
  88                debug("Can't get the usbphy register address\n");
  89                return -ENXIO;
  90        }
  91
  92        return 0;
  93}
  94#endif
  95
  96static void exynos5_usb3_phy_init(struct exynos_usb3_phy *phy)
  97{
  98        u32 reg;
  99
 100        /* enabling usb_drd phy */
 101        set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_EN);
 102
 103        /* Reset USB 3.0 PHY */
 104        writel(0x0, &phy->phy_reg0);
 105
 106        clrbits_le32(&phy->phy_param0,
 107                        /* Select PHY CLK source */
 108                        PHYPARAM0_REF_USE_PAD |
 109                        /* Set Loss-of-Signal Detector sensitivity */
 110                        PHYPARAM0_REF_LOSLEVEL_MASK);
 111        setbits_le32(&phy->phy_param0, PHYPARAM0_REF_LOSLEVEL);
 112
 113        writel(0x0, &phy->phy_resume);
 114
 115        /*
 116         * Setting the Frame length Adj value[6:1] to default 0x20
 117         * See xHCI 1.0 spec, 5.2.4
 118         */
 119        setbits_le32(&phy->link_system,
 120                        LINKSYSTEM_XHCI_VERSION_CONTROL |
 121                        LINKSYSTEM_FLADJ(0x20));
 122
 123        /* Set Tx De-Emphasis level */
 124        clrbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH_MASK);
 125        setbits_le32(&phy->phy_param1, PHYPARAM1_PCS_TXDEEMPH);
 126
 127        setbits_le32(&phy->phy_batchg, PHYBATCHG_UTMI_CLKSEL);
 128
 129        /* PHYTEST POWERDOWN Control */
 130        clrbits_le32(&phy->phy_test,
 131                        PHYTEST_POWERDOWN_SSP |
 132                        PHYTEST_POWERDOWN_HSP);
 133
 134        /* UTMI Power Control */
 135        writel(PHYUTMI_OTGDISABLE, &phy->phy_utmi);
 136
 137                /* Use core clock from main PLL */
 138        reg = PHYCLKRST_REFCLKSEL_EXT_REFCLK |
 139                /* Default 24Mhz crystal clock */
 140                PHYCLKRST_FSEL(FSEL_CLKSEL_24M) |
 141                PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF |
 142                PHYCLKRST_SSC_REFCLKSEL(0x88) |
 143                /* Force PortReset of PHY */
 144                PHYCLKRST_PORTRESET |
 145                /* Digital power supply in normal operating mode */
 146                PHYCLKRST_RETENABLEN |
 147                /* Enable ref clock for SS function */
 148                PHYCLKRST_REF_SSP_EN |
 149                /* Enable spread spectrum */
 150                PHYCLKRST_SSC_EN |
 151                /* Power down HS Bias and PLL blocks in suspend mode */
 152                PHYCLKRST_COMMONONN;
 153
 154        writel(reg, &phy->phy_clk_rst);
 155
 156        /* giving time to Phy clock to settle before resetting */
 157        udelay(10);
 158
 159        reg &= ~PHYCLKRST_PORTRESET;
 160        writel(reg, &phy->phy_clk_rst);
 161}
 162
 163static void exynos5_usb3_phy_exit(struct exynos_usb3_phy *phy)
 164{
 165        setbits_le32(&phy->phy_utmi,
 166                        PHYUTMI_OTGDISABLE |
 167                        PHYUTMI_FORCESUSPEND |
 168                        PHYUTMI_FORCESLEEP);
 169
 170        clrbits_le32(&phy->phy_clk_rst,
 171                        PHYCLKRST_REF_SSP_EN |
 172                        PHYCLKRST_SSC_EN |
 173                        PHYCLKRST_COMMONONN);
 174
 175        /* PHYTEST POWERDOWN Control to remove leakage current */
 176        setbits_le32(&phy->phy_test,
 177                        PHYTEST_POWERDOWN_SSP |
 178                        PHYTEST_POWERDOWN_HSP);
 179
 180        /* disabling usb_drd phy */
 181        set_usbdrd_phy_ctrl(POWER_USB_DRD_PHY_CTRL_DISABLE);
 182}
 183
 184void dwc3_set_mode(struct dwc3 *dwc3_reg, u32 mode)
 185{
 186        clrsetbits_le32(&dwc3_reg->g_ctl,
 187                        DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG),
 188                        DWC3_GCTL_PRTCAPDIR(mode));
 189}
 190
 191static void dwc3_core_soft_reset(struct dwc3 *dwc3_reg)
 192{
 193        /* Before Resetting PHY, put Core in Reset */
 194        setbits_le32(&dwc3_reg->g_ctl,
 195                        DWC3_GCTL_CORESOFTRESET);
 196
 197        /* Assert USB3 PHY reset */
 198        setbits_le32(&dwc3_reg->g_usb3pipectl[0],
 199                        DWC3_GUSB3PIPECTL_PHYSOFTRST);
 200
 201        /* Assert USB2 PHY reset */
 202        setbits_le32(&dwc3_reg->g_usb2phycfg,
 203                        DWC3_GUSB2PHYCFG_PHYSOFTRST);
 204
 205        mdelay(100);
 206
 207        /* Clear USB3 PHY reset */
 208        clrbits_le32(&dwc3_reg->g_usb3pipectl[0],
 209                        DWC3_GUSB3PIPECTL_PHYSOFTRST);
 210
 211        /* Clear USB2 PHY reset */
 212        clrbits_le32(&dwc3_reg->g_usb2phycfg,
 213                        DWC3_GUSB2PHYCFG_PHYSOFTRST);
 214
 215        /* After PHYs are stable we can take Core out of reset state */
 216        clrbits_le32(&dwc3_reg->g_ctl,
 217                        DWC3_GCTL_CORESOFTRESET);
 218}
 219
 220static int dwc3_core_init(struct dwc3 *dwc3_reg)
 221{
 222        u32 reg;
 223        u32 revision;
 224        unsigned int dwc3_hwparams1;
 225
 226        revision = readl(&dwc3_reg->g_snpsid);
 227        /* This should read as U3 followed by revision number */
 228        if ((revision & DWC3_GSNPSID_MASK) != 0x55330000) {
 229                puts("this is not a DesignWare USB3 DRD Core\n");
 230                return -EINVAL;
 231        }
 232
 233        dwc3_core_soft_reset(dwc3_reg);
 234
 235        dwc3_hwparams1 = readl(&dwc3_reg->g_hwparams1);
 236
 237        reg = readl(&dwc3_reg->g_ctl);
 238        reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 239        reg &= ~DWC3_GCTL_DISSCRAMBLE;
 240        switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc3_hwparams1)) {
 241        case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 242                reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 243                break;
 244        default:
 245                debug("No power optimization available\n");
 246        }
 247
 248        /*
 249         * WORKAROUND: DWC3 revisions <1.90a have a bug
 250         * where the device can fail to connect at SuperSpeed
 251         * and falls back to high-speed mode which causes
 252         * the device to enter a Connect/Disconnect loop
 253         */
 254        if ((revision & DWC3_REVISION_MASK) < 0x190a)
 255                reg |= DWC3_GCTL_U2RSTECN;
 256
 257        writel(reg, &dwc3_reg->g_ctl);
 258
 259        return 0;
 260}
 261
 262static int exynos_xhci_core_init(struct exynos_xhci *exynos)
 263{
 264        int ret;
 265
 266        exynos5_usb3_phy_init(exynos->usb3_phy);
 267
 268        ret = dwc3_core_init(exynos->dwc3_reg);
 269        if (ret) {
 270                debug("failed to initialize core\n");
 271                return -EINVAL;
 272        }
 273
 274        /* We are hard-coding DWC3 core to Host Mode */
 275        dwc3_set_mode(exynos->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
 276
 277        return 0;
 278}
 279
 280static void exynos_xhci_core_exit(struct exynos_xhci *exynos)
 281{
 282        exynos5_usb3_phy_exit(exynos->usb3_phy);
 283}
 284
 285int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
 286{
 287        struct exynos_xhci *ctx = &exynos;
 288        int ret;
 289
 290#ifdef CONFIG_OF_CONTROL
 291        exynos_usb3_parse_dt(gd->fdt_blob, ctx);
 292#else
 293        ctx->usb3_phy = (struct exynos_usb3_phy *)samsung_get_base_usb3_phy();
 294        ctx->hcd = (struct xhci_hccr *)samsung_get_base_usb_xhci();
 295#endif
 296
 297        ctx->dwc3_reg = (struct dwc3 *)((char *)(ctx->hcd) + DWC3_REG_OFFSET);
 298
 299#ifdef CONFIG_OF_CONTROL
 300        /* setup the Vbus gpio here */
 301        if (fdt_gpio_isvalid(&ctx->vbus_gpio) &&
 302            !fdtdec_setup_gpio(&ctx->vbus_gpio))
 303                gpio_direction_output(ctx->vbus_gpio.gpio, 1);
 304#endif
 305
 306        ret = exynos_xhci_core_init(ctx);
 307        if (ret) {
 308                puts("XHCI: failed to initialize controller\n");
 309                return -EINVAL;
 310        }
 311
 312        *hccr = (ctx->hcd);
 313        *hcor = (struct xhci_hcor *)((uint32_t) *hccr
 314                                + HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
 315
 316        debug("Exynos5-xhci: init hccr %x and hcor %x hc_length %d\n",
 317                (uint32_t)*hccr, (uint32_t)*hcor,
 318                (uint32_t)HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase)));
 319
 320        return 0;
 321}
 322
 323void xhci_hcd_stop(int index)
 324{
 325        struct exynos_xhci *ctx = &exynos;
 326
 327        exynos_xhci_core_exit(ctx);
 328}
 329