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12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15
16
17
18
19
20#define CONFIG_405GP 1
21#define CONFIG_CPCI405 1
22#define CONFIG_CPCI405_VER2 1
23
24#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
25
26#define CONFIG_BOARD_EARLY_INIT_F 1
27#define CONFIG_MISC_INIT_R 1
28
29#define CONFIG_SYS_CLK_FREQ 33330000
30
31#define CONFIG_BAUDRATE 9600
32#define CONFIG_BOOTDELAY 3
33
34#undef CONFIG_BOOTARGS
35#undef CONFIG_BOOTCOMMAND
36
37#define CONFIG_PREBOOT
38
39#define CONFIG_LOADS_ECHO 1
40#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
41
42#define CONFIG_PPC4xx_EMAC
43#define CONFIG_MII 1
44#define CONFIG_PHY_ADDR 0
45#define CONFIG_LXT971_NO_SLEEP 1
46#define CONFIG_RESET_PHY_R 1
47
48#undef CONFIG_HAS_ETH1
49
50#define CONFIG_RTC_M48T35A 1
51
52
53
54
55#define CONFIG_BOOTP_SUBNETMASK
56#define CONFIG_BOOTP_GATEWAY
57#define CONFIG_BOOTP_HOSTNAME
58#define CONFIG_BOOTP_BOOTPATH
59#define CONFIG_BOOTP_DNS
60#define CONFIG_BOOTP_DNS2
61#define CONFIG_BOOTP_SEND_HOSTNAME
62
63
64
65
66
67#include <config_cmd_default.h>
68
69#define CONFIG_CMD_DHCP
70#define CONFIG_CMD_PCI
71#define CONFIG_CMD_IRQ
72#define CONFIG_CMD_IDE
73#define CONFIG_CMD_FAT
74#define CONFIG_CMD_ELF
75#define CONFIG_CMD_DATE
76#define CONFIG_CMD_I2C
77#define CONFIG_CMD_MII
78#define CONFIG_CMD_PING
79#define CONFIG_CMD_BSP
80#define CONFIG_CMD_EEPROM
81
82#define CONFIG_MAC_PARTITION
83#define CONFIG_DOS_PARTITION
84
85#define CONFIG_SUPPORT_VFAT
86
87#undef CONFIG_AUTO_UPDATE
88
89#undef CONFIG_WATCHDOG
90
91#define CONFIG_SDRAM_BANK0 1
92
93
94
95
96#define CONFIG_SYS_LONGHELP
97
98#undef CONFIG_SYS_HUSH_PARSER
99
100#if defined(CONFIG_CMD_KGDB)
101#define CONFIG_SYS_CBSIZE 1024
102#else
103#define CONFIG_SYS_CBSIZE 256
104#endif
105#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
106#define CONFIG_SYS_MAXARGS 16
107#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
108
109#define CONFIG_SYS_DEVICE_NULLDEV 1
110
111#define CONFIG_SYS_CONSOLE_INFO_QUIET 1
112
113#define CONFIG_AUTO_COMPLETE 1
114
115#define CONFIG_SYS_MEMTEST_START 0x0400000
116#define CONFIG_SYS_MEMTEST_END 0x0C00000
117
118#define CONFIG_CONS_INDEX 1
119#define CONFIG_SYS_NS16550
120#define CONFIG_SYS_NS16550_SERIAL
121#define CONFIG_SYS_NS16550_REG_SIZE 1
122#define CONFIG_SYS_NS16550_CLK get_serial_clock()
123
124#undef CONFIG_SYS_EXT_SERIAL_CLOCK
125#define CONFIG_SYS_BASE_BAUD 691200
126
127
128#define CONFIG_SYS_BAUDRATE_TABLE \
129 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
130 57600, 115200, 230400, 460800, 921600 }
131
132#define CONFIG_SYS_LOAD_ADDR 0x100000
133#define CONFIG_SYS_EXTBDINFO 1
134
135#define CONFIG_LOOPW 1
136
137#define CONFIG_ZERO_BOOTDELAY_CHECK
138
139
140#define CONFIG_AUTOBOOT_KEYED 1
141#define CONFIG_AUTOBOOT_PROMPT \
142 "Autobooting in %d seconds\n", bootdelay
143#undef CONFIG_AUTOBOOT_DELAY_STR
144#undef CONFIG_AUTOBOOT_STOP_STR
145#define CONFIG_AUTOBOOT_STOP_STR2 "esdesd"
146
147#define CONFIG_VERSION_VARIABLE 1
148
149#define CONFIG_SYS_RX_ETH_BUFFER 16
150
151
152
153
154
155#define PCI_HOST_ADAPTER 0
156#define PCI_HOST_FORCE 1
157#define PCI_HOST_AUTO 2
158
159#define CONFIG_PCI
160#define CONFIG_PCI_INDIRECT_BRIDGE
161#define CONFIG_PCI_HOST PCI_HOST_AUTO
162#define CONFIG_PCI_PNP
163
164
165#define CONFIG_PCI_SCAN_SHOW
166
167#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1
168
169#define CONFIG_PCI_BOOTDELAY 0
170
171#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE
172#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405
173#define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406
174#define CONFIG_SYS_PCI_CLASSCODE 0x0b20
175#define CONFIG_SYS_PCI_PTM1LA (bd->bi_memstart)
176#define CONFIG_SYS_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1)
177#define CONFIG_SYS_PCI_PTM1PCI 0x00000000
178#define CONFIG_SYS_PCI_PTM2LA 0xffc00000
179#define CONFIG_SYS_PCI_PTM2MS 0xffc00001
180#define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize)
181
182#define CONFIG_PCI_4xx_PTM_OVERWRITE 1
183
184
185
186
187
188#undef CONFIG_IDE_8xx_DIRECT
189#undef CONFIG_IDE_LED
190#define CONFIG_IDE_RESET 1
191
192#define CONFIG_SYS_IDE_MAXBUS 1
193#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*1)
194
195#define CONFIG_SYS_ATA_BASE_ADDR 0xF0100000
196#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
197
198#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000
199#define CONFIG_SYS_ATA_REG_OFFSET 0x0000
200#define CONFIG_SYS_ATA_ALT_OFFSET 0x0000
201
202
203
204
205
206
207#define CONFIG_SYS_SDRAM_BASE 0x00000000
208#define CONFIG_SYS_FLASH_BASE 0xFFFC0000
209#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
210#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
211#define CONFIG_SYS_MALLOC_LEN (128 * 1024)
212
213
214
215
216
217
218#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
219
220
221
222#define CONFIG_SYS_MAX_FLASH_BANKS 2
223#define CONFIG_SYS_MAX_FLASH_SECT 256
224
225#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
226#define CONFIG_SYS_FLASH_WRITE_TOUT 500
227
228#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
229#define CONFIG_SYS_FLASH_ADDR0 0x5555
230#define CONFIG_SYS_FLASH_ADDR1 0x2AAA
231
232
233
234
235#define CONFIG_SYS_FLASH_READ0 0x0000
236#define CONFIG_SYS_FLASH_READ1 0x0001
237#define CONFIG_SYS_FLASH_READ2 0x0002
238
239#define CONFIG_SYS_FLASH_EMPTY_INFO
240
241#if 0
242
243
244
245#define CONFIG_ENV_IS_IN_NVRAM 1
246#define CONFIG_ENV_SIZE 0x0ff8
247#define CONFIG_ENV_ADDR \
248 (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8))
249
250#else
251
252#define CONFIG_ENV_IS_IN_EEPROM 1
253#define CONFIG_ENV_OFFSET 0x000
254#define CONFIG_ENV_SIZE 0x800
255
256#endif
257
258#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0200000
259#define CONFIG_SYS_NVRAM_SIZE (32*1024)
260#define CONFIG_SYS_VXWORKS_MAC_PTR (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900)
261
262
263
264
265#define CONFIG_SYS_I2C
266#define CONFIG_SYS_I2C_PPC4XX
267#define CONFIG_SYS_I2C_PPC4XX_CH0
268#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
269#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
270
271#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
272#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
273
274#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
275#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
276
277
278#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
279
280
281
282
283
284
285
286#define FLASH_BASE0_PRELIM 0xFF800000
287#define FLASH_BASE1_PRELIM 0xFFC00000
288
289
290
291
292
293
294#define CONFIG_SYS_EBC_PB0AP 0x92015480
295#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000
296
297
298#define CONFIG_SYS_EBC_PB1AP 0x92015480
299#define CONFIG_SYS_EBC_PB1CR 0xFF85A000
300
301
302#define CONFIG_SYS_EBC_PB2AP 0x010053C0
303#define CONFIG_SYS_EBC_PB2CR 0xF0018000
304#define CONFIG_SYS_LED_ADDR 0xF0000380
305
306
307#define CONFIG_SYS_EBC_PB3AP 0x010053C0
308#define CONFIG_SYS_EBC_PB3CR 0xF011A000
309
310
311
312#define CONFIG_SYS_EBC_PB4AP 0x01805680
313#define CONFIG_SYS_EBC_PB4CR 0xF0218000
314
315
316#define CONFIG_SYS_EBC_PB5AP 0x04005B80
317#define CONFIG_SYS_EBC_PB5CR 0xF0318000
318
319
320#define CONFIG_SYS_EBC_PB6AP 0x010053C0
321#define CONFIG_SYS_EBC_PB6CR 0xF041A000
322#define CONFIG_SYS_FPGA_BASE_ADDR 0xF0400000
323
324
325
326
327
328#define CONFIG_SYS_FPGA_MODE 0x00
329#define CONFIG_SYS_FPGA_STATUS 0x02
330#define CONFIG_SYS_FPGA_TS 0x04
331#define CONFIG_SYS_FPGA_TS_LOW 0x06
332#define CONFIG_SYS_FPGA_TS_CAP0 0x10
333#define CONFIG_SYS_FPGA_TS_CAP0_LOW 0x12
334#define CONFIG_SYS_FPGA_TS_CAP1 0x14
335#define CONFIG_SYS_FPGA_TS_CAP1_LOW 0x16
336#define CONFIG_SYS_FPGA_TS_CAP2 0x18
337#define CONFIG_SYS_FPGA_TS_CAP2_LOW 0x1a
338#define CONFIG_SYS_FPGA_TS_CAP3 0x1c
339#define CONFIG_SYS_FPGA_TS_CAP3_LOW 0x1e
340
341
342#define CONFIG_SYS_FPGA_MODE_CF_RESET 0x0001
343#define CONFIG_SYS_FPGA_MODE_DUART_RESET 0x0002
344#define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004
345#define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
346#define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR 0x1000
347#define CONFIG_SYS_FPGA_MODE_TS_CLEAR 0x2000
348
349
350#define CONFIG_SYS_FPGA_STATUS_DIP0 0x0001
351#define CONFIG_SYS_FPGA_STATUS_DIP1 0x0002
352#define CONFIG_SYS_FPGA_STATUS_DIP2 0x0004
353#define CONFIG_SYS_FPGA_STATUS_FLASH 0x0008
354#define CONFIG_SYS_FPGA_STATUS_TS_IRQ 0x1000
355
356#define CONFIG_SYS_FPGA_SPARTAN2 1
357#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024
358
359
360#define CONFIG_SYS_FPGA_PRG 0x04000000
361#define CONFIG_SYS_FPGA_CLK 0x02000000
362#define CONFIG_SYS_FPGA_DATA 0x01000000
363#define CONFIG_SYS_FPGA_INIT 0x00010000
364#define CONFIG_SYS_FPGA_DONE 0x00008000
365
366
367
368
369#define CONFIG_SYS_INIT_DCACHE_CS 7
370
371#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
372#define CONFIG_SYS_INIT_RAM_SIZE 0x2000
373#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
374#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
375
376#endif
377