1/* 2 * (C) Copyright 2003-2005 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8#ifndef __CONFIG_H 9#define __CONFIG_H 10 11/* 12 * High Level Configuration Options 13 * (easy to change) 14 */ 15 16#define CONFIG_MPC5200 1 /* This is a MPC5200 CPU */ 17#define CONFIG_ICECUBE 1 /* ... on IceCube board */ 18 19/* 20 * Valid values for CONFIG_SYS_TEXT_BASE are: 21 * 0xFFF00000 boot high (standard configuration) 22 * 0xFF000000 boot low for 16 MiB boards 23 * 0xFF800000 boot low for 8 MiB boards 24 * 0x00100000 boot from RAM (for testing only) 25 */ 26#ifndef CONFIG_SYS_TEXT_BASE 27#define CONFIG_SYS_TEXT_BASE 0xFFF00000 28#endif 29 30#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ 31 32#define CONFIG_HIGH_BATS 1 /* High BATs supported */ 33 34/* 35 * Serial console configuration 36 */ 37#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ 38#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ 39#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } 40 41 42/* 43 * PCI Mapping: 44 * 0x40000000 - 0x4fffffff - PCI Memory 45 * 0x50000000 - 0x50ffffff - PCI IO Space 46 */ 47#define CONFIG_PCI 48 49#if defined(CONFIG_PCI) 50#define CONFIG_PCI_PNP 1 51#define CONFIG_PCI_SCAN_SHOW 1 52#define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1 53 54#define CONFIG_PCI_MEM_BUS 0x40000000 55#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS 56#define CONFIG_PCI_MEM_SIZE 0x10000000 57 58#define CONFIG_PCI_IO_BUS 0x50000000 59#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS 60#define CONFIG_PCI_IO_SIZE 0x01000000 61#endif 62 63#define CONFIG_SYS_XLB_PIPELINING 1 64 65#define CONFIG_MII 1 66#define CONFIG_EEPRO100 1 67#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ 68#define CONFIG_NS8382X 1 69 70/* Partitions */ 71#define CONFIG_MAC_PARTITION 72#define CONFIG_DOS_PARTITION 73#define CONFIG_ISO_PARTITION 74 75/* USB */ 76#define CONFIG_USB_OHCI_NEW 77#define CONFIG_USB_STORAGE 78#define CONFIG_SYS_OHCI_BE_CONTROLLER 79#undef CONFIG_SYS_USB_OHCI_BOARD_INIT 80#define CONFIG_SYS_USB_OHCI_CPU_INIT 1 81#define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB 82#define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200" 83#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 84 85#define CONFIG_TIMESTAMP /* Print image info with timestamp */ 86 87 88/* 89 * BOOTP options 90 */ 91#define CONFIG_BOOTP_BOOTFILESIZE 92#define CONFIG_BOOTP_BOOTPATH 93#define CONFIG_BOOTP_GATEWAY 94#define CONFIG_BOOTP_HOSTNAME 95 96 97/* 98 * Command line configuration. 99 */ 100#include <config_cmd_default.h> 101 102#define CONFIG_CMD_EEPROM 103#define CONFIG_CMD_FAT 104#define CONFIG_CMD_I2C 105#define CONFIG_CMD_IDE 106#define CONFIG_CMD_NFS 107#define CONFIG_CMD_SNTP 108#define CONFIG_CMD_USB 109 110#if defined(CONFIG_PCI) 111#define CONFIG_CMD_PCI 112#endif 113 114 115#if (CONFIG_SYS_TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */ 116# define CONFIG_SYS_LOWBOOT 1 117# define CONFIG_SYS_LOWBOOT16 1 118#endif 119#if (CONFIG_SYS_TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */ 120#if defined(CONFIG_LITE5200B) 121# error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B 122#else 123# define CONFIG_SYS_LOWBOOT 1 124# define CONFIG_SYS_LOWBOOT08 1 125#endif 126#endif 127 128/* 129 * Autobooting 130 */ 131#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 132 133#define CONFIG_PREBOOT "echo;" \ 134 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 135 "echo" 136 137#undef CONFIG_BOOTARGS 138 139#define CONFIG_EXTRA_ENV_SETTINGS \ 140 "netdev=eth0\0" \ 141 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 142 "nfsroot=${serverip}:${rootpath}\0" \ 143 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 144 "addip=setenv bootargs ${bootargs} " \ 145 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 146 ":${hostname}:${netdev}:off panic=1\0" \ 147 "flash_nfs=run nfsargs addip;" \ 148 "bootm ${kernel_addr}\0" \ 149 "flash_self=run ramargs addip;" \ 150 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 151 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 152 "rootpath=/opt/eldk/ppc_82xx\0" \ 153 "bootfile=/tftpboot/MPC5200/uImage\0" \ 154 "" 155 156#define CONFIG_BOOTCOMMAND "run flash_self" 157 158/* 159 * IPB Bus clocking configuration. 160 */ 161#if defined(CONFIG_LITE5200B) 162#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ 163#else 164#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ 165#endif 166 167/* pass open firmware flat tree */ 168#define CONFIG_OF_LIBFDT 1 169#define CONFIG_OF_BOARD_SETUP 1 170 171#define OF_CPU "PowerPC,5200@0" 172#define OF_SOC "soc5200@f0000000" 173#define OF_TBCLK (bd->bi_busfreq / 4) 174#define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000" 175 176/* 177 * I2C configuration 178 */ 179#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ 180#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ 181 182#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ 183#define CONFIG_SYS_I2C_SLAVE 0x7F 184 185/* 186 * EEPROM configuration 187 */ 188#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ 189#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 190#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 191#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70 192 193/* 194 * Flash configuration 195 */ 196#if defined(CONFIG_LITE5200B) 197#define CONFIG_SYS_FLASH_BASE 0xFE000000 198#define CONFIG_SYS_FLASH_SIZE 0x01000000 199#if !defined(CONFIG_SYS_LOWBOOT) 200#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x01760000 + 0x00800000) 201#else /* CONFIG_SYS_LOWBOOT */ 202#if defined(CONFIG_SYS_LOWBOOT08) 203# error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B 204#endif 205#if defined(CONFIG_SYS_LOWBOOT16) 206#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x01060000) 207#endif 208#endif /* CONFIG_SYS_LOWBOOT */ 209#else /* !CONFIG_LITE5200B (IceCube)*/ 210#define CONFIG_SYS_FLASH_BASE 0xFF000000 211#define CONFIG_SYS_FLASH_SIZE 0x01000000 212#if !defined(CONFIG_SYS_LOWBOOT) 213#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00740000 + 0x00800000) 214#else /* CONFIG_SYS_LOWBOOT */ 215#if defined(CONFIG_SYS_LOWBOOT08) 216#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000 + 0x00800000) 217#endif 218#if defined(CONFIG_SYS_LOWBOOT16) 219#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) 220#endif 221#endif /* CONFIG_SYS_LOWBOOT */ 222#endif /* CONFIG_LITE5200B */ 223#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */ 224 225#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ 226 227#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ 228#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ 229 230#undef CONFIG_FLASH_16BIT /* Flash is 8-bit */ 231 232#if defined(CONFIG_LITE5200B) 233#define CONFIG_FLASH_CFI_DRIVER 234#define CONFIG_SYS_FLASH_CFI 235#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_CS1_START,CONFIG_SYS_CS0_START} 236#endif 237 238 239/* 240 * Environment settings 241 */ 242#define CONFIG_ENV_IS_IN_FLASH 1 243#define CONFIG_ENV_SIZE 0x10000 244#if defined(CONFIG_LITE5200B) 245#define CONFIG_ENV_SECT_SIZE 0x20000 246#else 247#define CONFIG_ENV_SECT_SIZE 0x10000 248#endif 249#define CONFIG_ENV_OVERWRITE 1 250 251/* 252 * Memory map 253 */ 254#define CONFIG_SYS_MBAR 0xF0000000 255#define CONFIG_SYS_SDRAM_BASE 0x00000000 256#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 257 258/* Use SRAM until RAM will be available */ 259#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM 260#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ 261 262 263#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 264#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 265 266#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 267#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 268# define CONFIG_SYS_RAMBOOT 1 269#endif 270 271#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ 272#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ 273#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 274 275/* 276 * Ethernet configuration 277 */ 278#define CONFIG_MPC5xxx_FEC 1 279#define CONFIG_MPC5xxx_FEC_MII100 280/* 281 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb 282 */ 283/* #define CONFIG_MPC5xxx_FEC_MII10 */ 284#define CONFIG_PHY_ADDR 0x00 285 286/* 287 * GPIO configuration 288 */ 289#ifdef CONFIG_MPC5200_DDR 290#define CONFIG_SYS_GPS_PORT_CONFIG 0x90000004 291#else 292#define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004 293#endif 294 295/* 296 * Miscellaneous configurable options 297 */ 298#define CONFIG_SYS_LONGHELP /* undef to save memory */ 299#if defined(CONFIG_CMD_KGDB) 300#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 301#else 302#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 303#endif 304#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 305#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 306#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 307 308#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 309#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ 310 311#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ 312#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ 313 314#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 315 316#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ 317#if defined(CONFIG_CMD_KGDB) 318# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 319#endif 320 321/* 322 * Various low-level settings 323 */ 324#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI 325#define CONFIG_SYS_HID0_FINAL HID0_ICE 326 327#if defined(CONFIG_LITE5200B) 328#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE 329#define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE 330#define CONFIG_SYS_CS1_CFG 0x00047800 331#define CONFIG_SYS_CS0_START (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE) 332#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE 333#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_CS0_START 334#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE 335#define CONFIG_SYS_BOOTCS_CFG 0x00047800 336#else /* IceCube aka Lite5200 */ 337#ifdef CONFIG_MPC5200_DDR 338 339#define CONFIG_SYS_BOOTCS_START (CONFIG_SYS_CS1_START + CONFIG_SYS_CS1_SIZE) 340#define CONFIG_SYS_BOOTCS_SIZE 0x00800000 341#define CONFIG_SYS_BOOTCS_CFG 0x00047801 342#define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE 343#define CONFIG_SYS_CS1_SIZE 0x00800000 344#define CONFIG_SYS_CS1_CFG 0x00047800 345 346#else /* !CONFIG_MPC5200_DDR */ 347 348#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE 349#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE 350#define CONFIG_SYS_BOOTCS_CFG 0x00047801 351#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE 352#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE 353 354#endif /* CONFIG_MPC5200_DDR */ 355#endif /*CONFIG_LITE5200B */ 356 357#define CONFIG_SYS_CS_BURST 0x00000000 358#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 359 360#define CONFIG_SYS_RESET_ADDRESS 0xff000000 361 362/*----------------------------------------------------------------------- 363 * USB stuff 364 *----------------------------------------------------------------------- 365 */ 366#define CONFIG_USB_CLOCK 0x0001BBBB 367#define CONFIG_USB_CONFIG 0x00001000 368 369/*----------------------------------------------------------------------- 370 * IDE/ATA stuff Supports IDE harddisk 371 *----------------------------------------------------------------------- 372 */ 373 374#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ 375 376#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 377#undef CONFIG_IDE_LED /* LED for ide not supported */ 378 379#define CONFIG_IDE_RESET /* reset for ide supported */ 380#define CONFIG_IDE_PREINIT 381 382#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 383#define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */ 384 385#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 386 387#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA 388 389/* Offset for data I/O */ 390#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) 391 392/* Offset for normal register accesses */ 393#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) 394 395/* Offset for alternate registers */ 396#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) 397 398/* Interval between registers */ 399#define CONFIG_SYS_ATA_STRIDE 4 400 401#define CONFIG_ATAPI 1 402 403#endif /* __CONFIG_H */ 404