1/* 2 * (C) Copyright 2000-2008 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * board/config.h - configuration options, board specific 10 */ 11 12#ifndef __CONFIG_H 13#define __CONFIG_H 14 15/* 16 * High Level Configuration Options 17 * (easy to change) 18 */ 19 20#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ 21#define CONFIG_TQM850L 1 /* ...on a TQM8xxL module */ 22 23#define CONFIG_SYS_TEXT_BASE 0x40000000 24 25#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 26#define CONFIG_SYS_SMC_RXBUFLEN 128 27#define CONFIG_SYS_MAXIDLE 10 28#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 29 30#define CONFIG_BOOTCOUNT_LIMIT 31 32#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 33 34#define CONFIG_BOARD_TYPES 1 /* support board types */ 35 36#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" 37 38#undef CONFIG_BOOTARGS 39 40#define CONFIG_EXTRA_ENV_SETTINGS \ 41 "netdev=eth0\0" \ 42 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 43 "nfsroot=${serverip}:${rootpath}\0" \ 44 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 45 "addip=setenv bootargs ${bootargs} " \ 46 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 47 ":${hostname}:${netdev}:off panic=1\0" \ 48 "flash_nfs=run nfsargs addip;" \ 49 "bootm ${kernel_addr}\0" \ 50 "flash_self=run ramargs addip;" \ 51 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 52 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 53 "rootpath=/opt/eldk/ppc_8xx\0" \ 54 "hostname=TQM850L\0" \ 55 "bootfile=TQM850L/uImage\0" \ 56 "fdt_addr=40040000\0" \ 57 "kernel_addr=40060000\0" \ 58 "ramdisk_addr=40200000\0" \ 59 "u-boot=TQM850L/u-image.bin\0" \ 60 "load=tftp 200000 ${u-boot}\0" \ 61 "update=prot off 40000000 +${filesize};" \ 62 "era 40000000 +${filesize};" \ 63 "cp.b 200000 40000000 ${filesize};" \ 64 "sete filesize;save\0" \ 65 "" 66#define CONFIG_BOOTCOMMAND "run flash_self" 67 68#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 69#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 70 71#undef CONFIG_WATCHDOG /* watchdog disabled */ 72 73#define CONFIG_STATUS_LED 1 /* Status LED enabled */ 74 75#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 76 77/* 78 * BOOTP options 79 */ 80#define CONFIG_BOOTP_SUBNETMASK 81#define CONFIG_BOOTP_GATEWAY 82#define CONFIG_BOOTP_HOSTNAME 83#define CONFIG_BOOTP_BOOTPATH 84#define CONFIG_BOOTP_BOOTFILESIZE 85 86 87#define CONFIG_MAC_PARTITION 88#define CONFIG_DOS_PARTITION 89 90#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 91 92/* 93 * Command line configuration. 94 */ 95#include <config_cmd_default.h> 96 97#define CONFIG_CMD_ASKENV 98#define CONFIG_CMD_DATE 99#define CONFIG_CMD_DHCP 100#define CONFIG_CMD_ELF 101#define CONFIG_CMD_EXT2 102#define CONFIG_CMD_IDE 103#define CONFIG_CMD_JFFS2 104#define CONFIG_CMD_NFS 105#define CONFIG_CMD_SNTP 106 107 108#define CONFIG_NETCONSOLE 109 110/* 111 * Miscellaneous configurable options 112 */ 113#define CONFIG_SYS_LONGHELP /* undef to save memory */ 114 115#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 116#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ 117 118#if defined(CONFIG_CMD_KGDB) 119#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 120#else 121#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 122#endif 123#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 124#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 125#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 126 127#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 128#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 129 130#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 131 132/* 133 * Low Level Configuration Settings 134 * (address mappings, register initial values, etc.) 135 * You should know what you are doing if you make changes here. 136 */ 137/*----------------------------------------------------------------------- 138 * Internal Memory Mapped Register 139 */ 140#define CONFIG_SYS_IMMR 0xFFF00000 141 142/*----------------------------------------------------------------------- 143 * Definitions for initial stack pointer and data area (in DPRAM) 144 */ 145#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 146#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 147#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 148#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 149 150/*----------------------------------------------------------------------- 151 * Start addresses for the final memory configuration 152 * (Set up by the startup code) 153 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 154 */ 155#define CONFIG_SYS_SDRAM_BASE 0x00000000 156#define CONFIG_SYS_FLASH_BASE 0x40000000 157#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 158#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 159#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 160 161/* 162 * For booting Linux, the board info and command line data 163 * have to be in the first 8 MB of memory, since this is 164 * the maximum mapped by the Linux kernel during initialization. 165 */ 166#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 167 168/*----------------------------------------------------------------------- 169 * FLASH organization 170 */ 171 172/* use CFI flash driver */ 173#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 174#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 175#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } 176#define CONFIG_SYS_FLASH_EMPTY_INFO 177#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 178#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 179#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ 180 181#define CONFIG_ENV_IS_IN_FLASH 1 182#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ 183#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ 184 185/* Address and size of Redundant Environment Sector */ 186#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) 187#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 188 189#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 190 191#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 192 193/*----------------------------------------------------------------------- 194 * Dynamic MTD partition support 195 */ 196#define CONFIG_CMD_MTDPARTS 197#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 198#define CONFIG_FLASH_CFI_MTD 199#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" 200 201#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ 202 "128k(dtb)," \ 203 "1664k(kernel)," \ 204 "2m(rootfs)," \ 205 "4m(data)" 206 207/*----------------------------------------------------------------------- 208 * Hardware Information Block 209 */ 210#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 211#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 212#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 213 214/*----------------------------------------------------------------------- 215 * Cache Configuration 216 */ 217#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 218#if defined(CONFIG_CMD_KGDB) 219#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 220#endif 221 222/*----------------------------------------------------------------------- 223 * SYPCR - System Protection Control 11-9 224 * SYPCR can only be written once after reset! 225 *----------------------------------------------------------------------- 226 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 227 */ 228#if defined(CONFIG_WATCHDOG) 229#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 230 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 231#else 232#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 233#endif 234 235/*----------------------------------------------------------------------- 236 * SIUMCR - SIU Module Configuration 11-6 237 *----------------------------------------------------------------------- 238 * PCMCIA config., multi-function pin tri-state 239 */ 240#ifndef CONFIG_CAN_DRIVER 241#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 242#else /* we must activate GPL5 in the SIUMCR for CAN */ 243#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 244#endif /* CONFIG_CAN_DRIVER */ 245 246/*----------------------------------------------------------------------- 247 * TBSCR - Time Base Status and Control 11-26 248 *----------------------------------------------------------------------- 249 * Clear Reference Interrupt Status, Timebase freezing enabled 250 */ 251#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 252 253/*----------------------------------------------------------------------- 254 * RTCSC - Real-Time Clock Status and Control Register 11-27 255 *----------------------------------------------------------------------- 256 */ 257#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 258 259/*----------------------------------------------------------------------- 260 * PISCR - Periodic Interrupt Status and Control 11-31 261 *----------------------------------------------------------------------- 262 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 263 */ 264#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 265 266/*----------------------------------------------------------------------- 267 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 268 *----------------------------------------------------------------------- 269 * Reset PLL lock status sticky bit, timer expired status bit and timer 270 * interrupt status bit 271 */ 272#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 273 274/*----------------------------------------------------------------------- 275 * SCCR - System Clock and reset Control Register 15-27 276 *----------------------------------------------------------------------- 277 * Set clock output, timebase and RTC source and divider, 278 * power management and some other internal clocks 279 */ 280#define SCCR_MASK SCCR_EBDF11 281#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 282 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 283 SCCR_DFALCD00) 284 285/*----------------------------------------------------------------------- 286 * PCMCIA stuff 287 *----------------------------------------------------------------------- 288 * 289 */ 290#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 291#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 292#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 293#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 294#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 295#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 296#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 297#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 298 299/*----------------------------------------------------------------------- 300 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 301 *----------------------------------------------------------------------- 302 */ 303 304#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ 305#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 306 307#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 308#undef CONFIG_IDE_LED /* LED for ide not supported */ 309#undef CONFIG_IDE_RESET /* reset for ide not supported */ 310 311#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 312#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 313 314#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 315 316#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 317 318/* Offset for data I/O */ 319#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 320 321/* Offset for normal register accesses */ 322#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 323 324/* Offset for alternate registers */ 325#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 326 327/*----------------------------------------------------------------------- 328 * 329 *----------------------------------------------------------------------- 330 * 331 */ 332#define CONFIG_SYS_DER 0 333 334/* 335 * Init Memory Controller: 336 * 337 * BR0/1 and OR0/1 (FLASH) 338 */ 339 340#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 341#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 342 343/* used to re-map FLASH both when starting from SRAM or FLASH: 344 * restrict access enough to keep SRAM working (if any) 345 * but not too much to meddle with FLASH accesses 346 */ 347#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 348#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 349 350/* 351 * FLASH timing: 352 */ 353#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 354 OR_SCY_3_CLK | OR_EHTR | OR_BI) 355 356#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 357#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 358#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 359 360#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 361#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 362#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 363 364/* 365 * BR2/3 and OR2/3 (SDRAM) 366 * 367 */ 368#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 369#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 370#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 371 372/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 373#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 374 375#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 376#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 377 378#ifndef CONFIG_CAN_DRIVER 379#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 380#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 381#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 382#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 383#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 384#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 385#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 386 BR_PS_8 | BR_MS_UPMB | BR_V ) 387#endif /* CONFIG_CAN_DRIVER */ 388 389/* 390 * Memory Periodic Timer Prescaler 391 * 392 * The Divider for PTA (refresh timer) configuration is based on an 393 * example SDRAM configuration (64 MBit, one bank). The adjustment to 394 * the number of chip selects (NCS) and the actually needed refresh 395 * rate is done by setting MPTPR. 396 * 397 * PTA is calculated from 398 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 399 * 400 * gclk CPU clock (not bus clock!) 401 * Trefresh Refresh cycle * 4 (four word bursts used) 402 * 403 * 4096 Rows from SDRAM example configuration 404 * 1000 factor s -> ms 405 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 406 * 4 Number of refresh cycles per period 407 * 64 Refresh cycle in ms per number of rows 408 * -------------------------------------------- 409 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 410 * 411 * 50 MHz => 50.000.000 / Divider = 98 412 * 66 Mhz => 66.000.000 / Divider = 129 413 * 80 Mhz => 80.000.000 / Divider = 156 414 */ 415 416#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 417#define CONFIG_SYS_MAMR_PTA 98 418 419/* 420 * For 16 MBit, refresh rates could be 31.3 us 421 * (= 64 ms / 2K = 125 / quad bursts). 422 * For a simpler initialization, 15.6 us is used instead. 423 * 424 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 425 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 426 */ 427#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 428#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 429 430/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 431#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 432#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 433 434/* 435 * MAMR settings for SDRAM 436 */ 437 438/* 8 column SDRAM */ 439#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 440 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 441 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 442/* 9 column SDRAM */ 443#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 444 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 445 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 446 447/* pass open firmware flat tree */ 448#define CONFIG_OF_LIBFDT 1 449#define CONFIG_OF_BOARD_SETUP 1 450#define CONFIG_HWCONFIG 1 451 452#endif /* __CONFIG_H */ 453