LXR uboot/include/configs/bf548-ezkit.h

   1/*
   2 * U-boot - Configuration file for BF548 STAMP board
   3 */
   4
   5#ifndef __CONFIG_BF548_EZKIT_H__
   6#define __CONFIG_BF548_EZKIT_H__
   7
   8#include <asm/config-pre.h>
   9
  10
  11/*
  12 * Processor Settings
  13 */
  14#define CONFIG_BFIN_CPU             bf548-0.0
  15#define CONFIG_BFIN_BOOT_MODE       BFIN_BOOT_PARA
  16
  17
  18/*
  19 * Clock Settings
  20 *      CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
  21 *      SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
  22 */
  23/* CONFIG_CLKIN_HZ is any value in Hz                                   */
  24#define CONFIG_CLKIN_HZ                 25000000
  25/* CLKIN_HALF controls the DF bit in PLL_CTL      0 = CLKIN             */
  26/*                                                1 = CLKIN / 2         */
  27#define CONFIG_CLKIN_HALF               0
  28/* PLL_BYPASS controls the BYPASS bit in PLL_CTL  0 = do not bypass     */
  29/*                                                1 = bypass PLL        */
  30#define CONFIG_PLL_BYPASS               0
  31/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL              */
  32/* Values can range from 0-63 (where 0 means 64)                        */
  33#define CONFIG_VCO_MULT                 21
  34/* CCLK_DIV controls the core clock divider                             */
  35/* Values can be 1, 2, 4, or 8 ONLY                                     */
  36#define CONFIG_CCLK_DIV                 1
  37/* SCLK_DIV controls the system clock divider                           */
  38/* Values can range from 1-15                                           */
  39#define CONFIG_SCLK_DIV                 4
  40
  41
  42/*
  43 * Memory Settings
  44 */
  45#define CONFIG_MEM_ADD_WDTH     10
  46#define CONFIG_MEM_SIZE         64
  47
  48#define CONFIG_EBIU_DDRCTL0_VAL 0x218A83FE
  49#define CONFIG_EBIU_DDRCTL1_VAL 0x20022222
  50#define CONFIG_EBIU_DDRCTL2_VAL 0x00000021
  51
  52/* Default EZ-Kit bank mapping:
  53 *      Async Bank 0 - 32MB Burst Flash
  54 *      Async Bank 1 - Ethernet
  55 *      Async Bank 2 - Nothing
  56 *      Async Bank 3 - Nothing
  57 */
  58#define CONFIG_EBIU_AMGCTL_VAL  0xFF
  59#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
  60#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
  61#define CONFIG_EBIU_FCTL_VAL    (BCLK_4)
  62#define CONFIG_EBIU_MODE_VAL    (B0MODE_FLASH)
  63
  64#define CONFIG_SYS_MONITOR_LEN  (1024 * 1024)
  65#define CONFIG_SYS_MALLOC_LEN   (768 * 1024)
  66
  67
  68/*
  69 * Network Settings
  70 */
  71#define ADI_CMDS_NETWORK        1
  72#define CONFIG_SMC911X  1
  73#define CONFIG_SMC911X_BASE     0x24000000
  74#define CONFIG_SMC911X_16_BIT
  75#define CONFIG_HOSTNAME         bf548-ezkit
  76/* Uncomment next line to use fixed MAC address */
  77/* #define CONFIG_ETHADDR       02:80:ad:20:31:e8 */
  78
  79
  80/*
  81 * Flash Settings
  82 */
  83#define CONFIG_FLASH_CFI_DRIVER
  84#define CONFIG_SYS_FLASH_BASE           0x20000000
  85#define CONFIG_SYS_FLASH_CFI
  86#define CONFIG_SYS_FLASH_PROTECTION
  87#define CONFIG_SYS_MAX_FLASH_BANKS      1
  88#define CONFIG_SYS_MAX_FLASH_SECT       259
  89
  90
  91/*
  92 * SPI Settings
  93 */
  94#define CONFIG_BFIN_SPI
  95#define CONFIG_ENV_SPI_MAX_HZ   30000000
  96#define CONFIG_SF_DEFAULT_SPEED 30000000
  97#define CONFIG_SPI_FLASH
  98#define CONFIG_SPI_FLASH_STMICRO
  99
 100
 101/*
 102 * Env Storage Settings
 103 */
 104#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER)
 105#define CONFIG_ENV_IS_IN_SPI_FLASH
 106#define CONFIG_ENV_OFFSET       0x10000
 107#define CONFIG_ENV_SIZE         0x2000
 108#define CONFIG_ENV_SECT_SIZE    0x10000
 109#define CONFIG_ENV_IS_EMBEDDED_IN_LDR
 110#elif (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
 111#define CONFIG_ENV_IS_IN_NAND
 112#define CONFIG_ENV_OFFSET       0x60000
 113#define CONFIG_ENV_SIZE         0x20000
 114#else
 115/* The BF548-EZKIT uses a top boot flash */
 116#define CONFIG_ENV_IS_IN_FLASH  1
 117#define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + CONFIG_ENV_OFFSET)
 118#define CONFIG_ENV_OFFSET       (0x1000000 - CONFIG_ENV_SECT_SIZE)
 119#define CONFIG_ENV_SIZE         CONFIG_ENV_SECT_SIZE
 120#define CONFIG_ENV_SECT_SIZE    0x8000
 121#endif
 122
 123/*
 124 * NAND Settings
 125 */
 126#if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_NAND)
 127#define CONFIG_BFIN_NFC_CTL_VAL        0x0033
 128#define CONFIG_BFIN_NFC_BOOTROM_ECC
 129#define CONFIG_DRIVER_NAND_BFIN
 130#define CONFIG_SYS_NAND_BASE           0 /* not actually used */
 131#define CONFIG_SYS_MAX_NAND_DEVICE     1
 132#endif
 133
 134/*
 135 * I2C Settings
 136 */
 137#define CONFIG_BFIN_TWI_I2C     1
 138#define CONFIG_HARD_I2C         1
 139
 140
 141/*
 142 * SATA
 143 */
 144#if !defined(__ADSPBF544__)
 145#define CONFIG_LIBATA
 146#define CONFIG_SYS_SATA_MAX_DEVICE 1
 147#define CONFIG_LBA48
 148#define CONFIG_PATA_BFIN
 149#define CONFIG_BFIN_ATAPI_BASE_ADDR     0xFFC03800
 150#define CONFIG_BFIN_ATA_MODE    XFER_PIO_4
 151#endif
 152
 153
 154/*
 155 * SDH Settings
 156 */
 157#if !defined(__ADSPBF544__)
 158#define CONFIG_GENERIC_MMC
 159#define CONFIG_MMC
 160#define CONFIG_BFIN_SDH
 161#endif
 162
 163
 164/*
 165 * USB Settings
 166 */
 167#if !defined(__ADSPBF544__)
 168#define CONFIG_USB
 169#define CONFIG_MUSB_HCD
 170#define CONFIG_USB_BLACKFIN
 171#define CONFIG_USB_STORAGE
 172#define CONFIG_MUSB_TIMEOUT 100000
 173#endif
 174
 175
 176/*
 177 * Misc Settings
 178 */
 179#define CONFIG_BOARD_EARLY_INIT_F
 180#define CONFIG_BOARD_SIZE_LIMIT $$(( 512 * 1024 ))
 181#define CONFIG_RTC_BFIN
 182#define CONFIG_UART_CONSOLE     1
 183#define CONFIG_BFIN_SPI_IMG_SIZE 0x50000
 184#define CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED
 185
 186#define CONFIG_ADI_GPIO2
 187
 188#undef CONFIG_VIDEO
 189#ifdef CONFIG_VIDEO
 190#define EASYLOGO_HEADER < asm/bfin_logo_230x230_gzip.h >
 191#define CONFIG_DEB_DMA_URGENT
 192#endif
 193
 194/* Define if want to do post memory test */
 195#undef CONFIG_POST
 196#ifdef CONFIG_POST
 197#define CONFIG_POST_BSPEC1_GPIO_LEDS \
 198        GPIO_PG6, GPIO_PG7, GPIO_PG8, GPIO_PG9, GPIO_PG10, GPIO_PG11,
 199#define CONFIG_POST_BSPEC2_GPIO_BUTTONS \
 200        GPIO_PB8, GPIO_PB9, GPIO_PB10, GPIO_PB11
 201#define CONFIG_POST_BSPEC2_GPIO_NAMES \
 202        13, 12, 11, 10,
 203#define CONFIG_SYS_POST_FLASH_START     10
 204#define CONFIG_SYS_POST_FLASH_END       127
 205#endif
 206
 207
 208/*
 209 * Pull in common ADI header for remaining command/environment setup
 210 */
 211#include <configs/bfin_adi_common.h>
 212
 213#endif
 214