1/* 2 * Copyright (C) 2006 Embedded Planet, LLC. 3 * 4 * U-Boot configuration for Embedded Planet EP82xxM boards. 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9#ifndef __CONFIG_H 10#define __CONFIG_H 11 12#define CPU_ID_STR "MPC8270" 13 14#define CONFIG_EP82XXM /* Embedded Planet EP82xxM H 1.0 board */ 15 /* 256MB SDRAM / 64MB FLASH */ 16 17#define CONFIG_SYS_TEXT_BASE 0xFFF00000 18 19#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ 20 21/* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */ 22#define CONFIG_ENV_OVERWRITE 23 24/* 25 * Select serial console configuration 26 * 27 * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then 28 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 29 * for SCC). 30 */ 31#define CONFIG_CONS_ON_SMC /* Console is on SMC */ 32#undef CONFIG_CONS_ON_SCC /* It's not on SCC */ 33#undef CONFIG_CONS_NONE /* It's not on external UART */ 34#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */ 35 36#define CONFIG_SYS_BCSR 0xFA000000 37 38/* 39 * Select ethernet configuration 40 * 41 * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, 42 * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for 43 * SCC, 1-3 for FCC) 44 * 45 * If CONFIG_ETHER_NONE is defined, then either the ethernet routines 46 * must be defined elsewhere (as for the console), or CONFIG_CMD_NET 47 * must be unset. 48 */ 49#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ 50#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ 51#undef CONFIG_ETHER_NONE /* No external Ethernet */ 52 53 54#define CONFIG_ETHER_ON_FCC2 55#define CONFIG_ETHER_ON_FCC3 56 57#define CONFIG_SYS_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) 58#define CONFIG_SYS_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK16) 59#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) 60#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) 61 62#define CONFIG_SYS_CPMFCR_RAMTYPE 0 63#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) 64 65#define CONFIG_MII /* MII PHY management */ 66#define CONFIG_BITBANGMII /* Bit-banged MDIO interface */ 67 68/* 69 * GPIO pins used for bit-banged MII communications 70 */ 71#define MDIO_PORT 0 /* Not used - implemented in BCSR */ 72 73#define MDIO_ACTIVE (*(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFB) 74#define MDIO_TRISTATE (*(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x04) 75#define MDIO_READ (*(vu_char *)(CONFIG_SYS_BCSR + 8) & 1) 76 77#define MDIO(bit) if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x01; \ 78 else *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFE 79 80#define MDC(bit) if(bit) *(vu_char *)(CONFIG_SYS_BCSR + 8) |= 0x02; \ 81 else *(vu_char *)(CONFIG_SYS_BCSR + 8) &= 0xFD 82 83#define MIIDELAY udelay(1) 84 85 86#ifndef CONFIG_8260_CLKIN 87#define CONFIG_8260_CLKIN 66000000 /* in Hz */ 88#endif 89 90#define CONFIG_BAUDRATE 115200 91 92#define CONFIG_SYS_VXWORKS_MAC_PTR 0x4300 /* Pass Ethernet MAC to VxWorks */ 93 94 95/* 96 * BOOTP options 97 */ 98#define CONFIG_BOOTP_BOOTFILESIZE 99#define CONFIG_BOOTP_BOOTPATH 100#define CONFIG_BOOTP_GATEWAY 101#define CONFIG_BOOTP_HOSTNAME 102 103 104/* 105 * Command line configuration. 106 */ 107#include <config_cmd_default.h> 108 109 110#define CONFIG_CMD_DHCP 111#define CONFIG_CMD_ECHO 112#define CONFIG_CMD_I2C 113#define CONFIG_CMD_IMMAP 114#define CONFIG_CMD_MII 115#define CONFIG_CMD_PING 116#define CONFIG_CMD_DATE 117#define CONFIG_CMD_DTT 118#define CONFIG_CMD_EEPROM 119#define CONFIG_CMD_PCI 120#define CONFIG_CMD_DIAG 121 122 123#define CONFIG_ETHADDR 00:10:EC:00:88:65 124#define CONFIG_HAS_ETH1 125#define CONFIG_ETH1ADDR 00:10:EC:80:88:65 126#define CONFIG_IPADDR 10.0.0.245 127#define CONFIG_HOSTNAME EP82xxM 128#define CONFIG_SERVERIP 10.0.0.26 129#define CONFIG_GATEWAYIP 10.0.0.1 130#define CONFIG_NETMASK 255.255.255.0 131#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 132#define CONFIG_ENV_IN_OWN_SECT 1 133#define CONFIG_AUTO_COMPLETE 1 134#define CONFIG_EXTRA_ENV_SETTINGS "ethprime=FCC3" 135 136#if defined(CONFIG_CMD_KGDB) 137#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ 138#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ 139#undef CONFIG_KGDB_NONE /* define if kgdb on something else */ 140#define CONFIG_KGDB_INDEX 1 /* which serial channel for kgdb */ 141#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */ 142#endif 143 144#define CONFIG_BZIP2 /* include support for bzip2 compressed images */ 145#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ 146 147/* 148 * Miscellaneous configurable options 149 */ 150#define CONFIG_SYS_HUSH_PARSER 151#define CONFIG_SYS_LONGHELP /* undef to save memory */ 152#define CONFIG_SYS_PROMPT "ep82xxm=> " /* Monitor Command Prompt */ 153#if defined(CONFIG_CMD_KGDB) 154#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 155#else 156#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 157#endif 158#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 159#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 160#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 161 162#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ 163#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ 164 165#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 166 167#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } 168 169/*----------------------------------------------------------------------- 170 * Environment 171 *----------------------------------------------------------------------*/ 172/* 173 * Define here the location of the environment variables (FLASH or EEPROM). 174 * Note: DENX encourages to use redundant environment in FLASH. 175 */ 176#if 1 177#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ 178#else 179#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ 180#endif 181 182/*----------------------------------------------------------------------- 183 * FLASH related 184 *----------------------------------------------------------------------*/ 185#define CONFIG_SYS_FLASH_BASE 0xFC000000 186#define CONFIG_SYS_FLASH_CFI 187#define CONFIG_FLASH_CFI_DRIVER 188#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ 189#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ 190#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector in flinfo */ 191 192#ifdef CONFIG_ENV_IS_IN_FLASH 193#define CONFIG_ENV_SECT_SIZE 0x20000 194#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 195#endif /* CONFIG_ENV_IS_IN_FLASH */ 196 197/*----------------------------------------------------------------------- 198 * I2C 199 *----------------------------------------------------------------------*/ 200/* EEPROM Configuration */ 201#define CONFIG_SYS_EEPROM_SIZE 0x1000 202#define CONFIG_SYS_I2C_EEPROM_ADDR 0x54 203#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 204#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 205#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 206 207#ifdef CONFIG_ENV_IS_IN_EEPROM 208#define CONFIG_ENV_SIZE 0x200 /* Size of Environment vars */ 209#define CONFIG_ENV_OFFSET 0x0 210#endif /* CONFIG_ENV_IS_IN_EEPROM */ 211 212/* RTC Configuration */ 213#define CONFIG_RTC_M41T11 1 /* uses a M41T81 */ 214#define CONFIG_SYS_I2C_RTC_ADDR 0x68 215#define CONFIG_M41T11_BASE_YEAR 1900 216 217/* I2C SYSMON (LM75) */ 218#define CONFIG_DTT_LM75 1 219#define CONFIG_DTT_SENSORS {0} 220#define CONFIG_SYS_DTT_MAX_TEMP 70 221#define CONFIG_SYS_DTT_LOW_TEMP -30 222#define CONFIG_SYS_DTT_HYSTERESIS 3 223 224/*----------------------------------------------------------------------- 225 * NVRAM Configuration 226 *----------------------------------------------------------------------- 227 */ 228#define CONFIG_SYS_NVRAM_BASE_ADDR 0xFA080000 229#define CONFIG_SYS_NVRAM_SIZE (128*1024)-16 230 231 232/*----------------------------------------------------------------------- 233 * PCI stuff 234 *----------------------------------------------------------------------- 235 */ 236/* General PCI */ 237#define CONFIG_PCI /* include pci support */ 238#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 239#define CONFIG_PCI_PNP /* do pci plug-and-play */ 240#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ 241#define CONFIG_PCI_BOOTDELAY 0 242 243/* PCI Memory map (if different from default map */ 244#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */ 245#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ 246#define CONFIG_SYS_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \ 247 PICMR_PREFETCH_EN) 248 249/* 250 * These are the windows that allow the CPU to access PCI address space. 251 * All three PCI master windows, which allow the CPU to access PCI 252 * prefetch, non prefetch, and IO space (see below), must all fit within 253 * these windows. 254 */ 255 256/* 257 * Master window that allows the CPU to access PCI Memory (prefetch). 258 * This window will be setup with the second set of Outbound ATU registers 259 * in the bridge. 260 */ 261 262#define CONFIG_SYS_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ 263#define CONFIG_SYS_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ 264#define CONFIG_SYS_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL 265#define CONFIG_SYS_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */ 266#define CONFIG_SYS_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN) 267 268/* 269 * Master window that allows the CPU to access PCI Memory (non-prefetch). 270 * This window will be setup with the second set of Outbound ATU registers 271 * in the bridge. 272 */ 273 274#define CONFIG_SYS_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */ 275#define CONFIG_SYS_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */ 276#define CONFIG_SYS_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL 277#define CONFIG_SYS_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */ 278#define CONFIG_SYS_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) 279 280/* 281 * Master window that allows the CPU to access PCI IO space. 282 * This window will be setup with the first set of Outbound ATU registers 283 * in the bridge. 284 */ 285 286#define CONFIG_SYS_PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */ 287#define CONFIG_SYS_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */ 288#define CONFIG_SYS_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL 289#define CONFIG_SYS_PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */ 290#define CONFIG_SYS_POCMR2_MASK_ATTRIB (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO) 291 292 293/* PCIBR0 - for PCI IO*/ 294#define CONFIG_SYS_PCI_MSTR0_LOCAL CONFIG_SYS_PCI_MSTR_IO_LOCAL /* Local base */ 295#define CONFIG_SYS_PCIMSK0_MASK ~(CONFIG_SYS_PCI_MSTR_IO_SIZE - 1U) /* Size of window */ 296/* PCIBR1 - prefetch and non-prefetch regions joined together */ 297#define CONFIG_SYS_PCI_MSTR1_LOCAL CONFIG_SYS_PCI_MSTR_MEM_LOCAL 298#define CONFIG_SYS_PCIMSK1_MASK ~(CONFIG_SYS_PCI_MSTR_MEM_SIZE + CONFIG_SYS_PCI_MSTR_MEMIO_SIZE - 1U) 299 300 301#define CONFIG_SYS_DIRECT_FLASH_TFTP 302 303#if defined(CONFIG_CMD_JFFS2) 304#define CONFIG_SYS_JFFS2_FIRST_BANK 0 305#define CONFIG_SYS_JFFS2_NUM_BANKS CONFIG_SYS_MAX_FLASH_BANKS 306#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0 307#define CONFIG_SYS_JFFS2_LAST_SECTOR 62 308#define CONFIG_SYS_JFFS2_SORT_FRAGMENTS 309#define CONFIG_SYS_JFFS_CUSTOM_PART 310#endif 311 312#if defined(CONFIG_CMD_I2C) 313#define CONFIG_HARD_I2C 1 /* To enable I2C support */ 314#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ 315#define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave address */ 316#endif 317 318#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 319#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 320#define CONFIG_SYS_RAMBOOT 321#endif 322 323#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 256KB for Monitor */ 324 325#define CONFIG_SYS_DEFAULT_IMMR 0x00010000 326#define CONFIG_SYS_IMMR 0xF0000000 327 328#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 329#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */ 330#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 331#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 332 333 334/* Hard reset configuration word */ 335#define CONFIG_SYS_HRCW_MASTER 0 /*0x1C800641*/ /* Not used - provided by CPLD */ 336/* No slaves */ 337#define CONFIG_SYS_HRCW_SLAVE1 0 338#define CONFIG_SYS_HRCW_SLAVE2 0 339#define CONFIG_SYS_HRCW_SLAVE3 0 340#define CONFIG_SYS_HRCW_SLAVE4 0 341#define CONFIG_SYS_HRCW_SLAVE5 0 342#define CONFIG_SYS_HRCW_SLAVE6 0 343#define CONFIG_SYS_HRCW_SLAVE7 0 344 345#define CONFIG_SYS_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ 346#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 347 348#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ 349#if defined(CONFIG_CMD_KGDB) 350#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 351#endif 352 353#define CONFIG_SYS_HID0_INIT 0 354#define CONFIG_SYS_HID0_FINAL 0 355 356#define CONFIG_SYS_HID2 0 357 358#define CONFIG_SYS_SIUMCR 0x02610000 359#define CONFIG_SYS_SYPCR 0xFFFF0689 360#define CONFIG_SYS_BCR 0x8080E000 361#define CONFIG_SYS_SCCR 0x00000001 362 363#define CONFIG_SYS_RMR 0 364#define CONFIG_SYS_TMCNTSC 0x000000C3 365#define CONFIG_SYS_PISCR 0x00000083 366#define CONFIG_SYS_RCCR 0 367 368#define CONFIG_SYS_MPTPR 0x0A00 369#define CONFIG_SYS_PSDMR 0xC432246E 370#define CONFIG_SYS_PSRT 0x32 371 372#define CONFIG_SYS_SDRAM_BASE 0x00000000 373#define CONFIG_SYS_SDRAM_BR (CONFIG_SYS_SDRAM_BASE | 0x00000041) 374#define CONFIG_SYS_SDRAM_OR 0xF0002900 375 376#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x00001801) 377#define CONFIG_SYS_OR0_PRELIM 0xFC000882 378#define CONFIG_SYS_BR4_PRELIM (CONFIG_SYS_BCSR | 0x00001001) 379#define CONFIG_SYS_OR4_PRELIM 0xFFF00050 380 381#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 382 383#endif /* __CONFIG_H */ 384