LXR uboot/include/configs/ethernut5.h

   1/*
   2 * (C) Copyright 2011
   3 * egnite GmbH <info@egnite.de>
   4 *
   5 * Configuation settings for Ethernut 5 with AT91SAM9XE.
   6 *
   7 * SPDX-License-Identifier:     GPL-2.0+
   8 */
   9
  10#ifndef __CONFIG_H
  11#define __CONFIG_H
  12
  13#include <asm/hardware.h>
  14
  15#define CONFIG_SYS_GENERIC_BOARD
  16
  17/* The first stage boot loader expects u-boot running at this address. */
  18#define CONFIG_SYS_TEXT_BASE    0x27000000      /* 16MB available */
  19
  20/* The first stage boot loader takes care of low level initialization. */
  21#define CONFIG_SKIP_LOWLEVEL_INIT
  22
  23/* Set our official architecture number. */
  24#define MACH_TYPE_ETHERNUT5 1971
  25#define CONFIG_MACH_TYPE MACH_TYPE_ETHERNUT5
  26
  27/* CPU information */
  28#define CONFIG_DISPLAY_CPUINFO          /* Display at console. */
  29#define CONFIG_ARCH_CPU_INIT
  30
  31/* ARM asynchronous clock */
  32#define CONFIG_SYS_AT91_SLOW_CLOCK      32768   /* slow clock xtal */
  33#define CONFIG_SYS_AT91_MAIN_CLOCK      18432000 /* 18.432 MHz crystal */
  34
  35/* 32kB internal SRAM */
  36#define CONFIG_SRAM_BASE        0x00300000 /*AT91SAM9XE_SRAM_BASE */
  37#define CONFIG_SRAM_SIZE        (32 << 10)
  38#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SRAM_BASE + CONFIG_SRAM_SIZE - \
  39                                GENERATED_GBL_DATA_SIZE)
  40
  41/* 128MB SDRAM in 1 bank */
  42#define CONFIG_NR_DRAM_BANKS            1
  43#define CONFIG_SYS_SDRAM_BASE           0x20000000
  44#define CONFIG_SYS_SDRAM_SIZE           (128 << 20)
  45#define CONFIG_SYS_LOAD_ADDR            CONFIG_SYS_SDRAM_BASE
  46#define CONFIG_LOADADDR                 CONFIG_SYS_LOAD_ADDR
  47#define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + (1 << 20))
  48#define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE
  49#define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_TEXT_BASE \
  50                                        - CONFIG_SYS_MALLOC_LEN)
  51
  52/* 512kB on-chip NOR flash */
  53# define CONFIG_SYS_MAX_FLASH_BANKS     1
  54# define CONFIG_SYS_FLASH_BASE          0x00200000 /* AT91SAM9XE_FLASH_BASE */
  55# define CONFIG_AT91_EFLASH
  56# define CONFIG_SYS_MAX_FLASH_SECT      32
  57# define CONFIG_SYS_FLASH_PROTECTION    /* First stage loader in sector 0 */
  58# define CONFIG_EFLASH_PROTSECTORS      1
  59
  60/* 512kB DataFlash at NPCS0 */
  61#define CONFIG_SYS_MAX_DATAFLASH_BANKS  1
  62#define CONFIG_HAS_DATAFLASH
  63#define CONFIG_SPI_FLASH
  64#define CONFIG_SPI_FLASH_ATMEL
  65#define CONFIG_ATMEL_DATAFLASH_SPI
  66#define CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0     0xC0000000
  67#define DATAFLASH_TCSS                  (0x1a << 16)
  68#define DATAFLASH_TCHS                  (0x1 << 24)
  69
  70#define CONFIG_ENV_IS_IN_SPI_FLASH
  71#define CONFIG_ENV_OFFSET               0x3DE000
  72#define CONFIG_ENV_SECT_SIZE            (132 << 10)
  73#define CONFIG_ENV_SIZE                 CONFIG_ENV_SECT_SIZE
  74#define CONFIG_ENV_ADDR                 (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \
  75                                        + CONFIG_ENV_OFFSET)
  76#define CONFIG_SYS_MONITOR_BASE         (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 \
  77                                        + 0x042000)
  78
  79/* SPI */
  80#define CONFIG_ATMEL_SPI
  81#define CONFIG_SYS_SPI_WRITE_TOUT       (5 * CONFIG_SYS_HZ)
  82#define AT91_SPI_CLK                    15000000
  83
  84/* Serial port */
  85#define CONFIG_ATMEL_USART
  86#define CONFIG_USART3                   /* USART 3 is DBGU */
  87#define CONFIG_BAUDRATE                 115200
  88#define CONFIG_USART_BASE               ATMEL_BASE_DBGU
  89#define CONFIG_USART_ID                 ATMEL_ID_SYS
  90
  91/* Misc. hardware drivers */
  92#define CONFIG_AT91_GPIO
  93
  94/* Command line configuration */
  95#include <config_cmd_default.h>
  96#undef CONFIG_CMD_BDI
  97#undef CONFIG_CMD_FPGA
  98#undef CONFIG_CMD_LOADS
  99
 100#define CONFIG_CMD_JFFS2
 101#define CONFIG_CMD_MII
 102#define CONFIG_CMD_MTDPARTS
 103#define CONFIG_CMD_NAND
 104#define CONFIG_CMD_SPI
 105
 106#ifdef MINIMAL_LOADER
 107#undef CONFIG_CMD_CONSOLE
 108#undef CONFIG_CMD_EDITENV
 109#undef CONFIG_CMD_IMI
 110#undef CONFIG_CMD_ITEST
 111#undef CONFIG_CMD_IMLS
 112#undef CONFIG_CMD_LOADB
 113#undef CONFIG_CMD_LOADS
 114#undef CONFIG_CMD_NFS
 115#undef CONFIG_CMD_SETGETDCR
 116#undef CONFIG_CMD_XIMG
 117#else
 118#define CONFIG_CMD_ASKENV
 119#define CONFIG_CMD_BSP
 120#define CONFIG_CMD_CACHE
 121#define CONFIG_CMD_CDP
 122#define CONFIG_CMD_DATE
 123#define CONFIG_CMD_DHCP
 124#define CONFIG_CMD_DNS
 125#define CONFIG_CMD_EXT2
 126#define CONFIG_CMD_FAT
 127#define CONFIG_CMD_I2C
 128#define CONFIG_CMD_MMC
 129#define CONFIG_CMD_PING
 130#define CONFIG_CMD_RARP
 131#define CONFIG_CMD_REISER
 132#define CONFIG_CMD_SAVES
 133#define CONFIG_CMD_SETEXPR
 134#define CONFIG_CMD_SF
 135#define CONFIG_CMD_SNTP
 136#define CONFIG_CMD_UBI
 137#define CONFIG_CMD_UBIFS
 138#define CONFIG_CMD_UNZIP
 139#define CONFIG_CMD_USB
 140#endif
 141
 142/* NAND flash */
 143#ifdef CONFIG_CMD_NAND
 144#define CONFIG_SYS_MAX_NAND_DEVICE      1
 145#define CONFIG_SYS_NAND_BASE            0x40000000
 146#define CONFIG_SYS_NAND_DBW_8
 147#define CONFIG_NAND_ATMEL
 148/* our ALE is AD21 */
 149#define CONFIG_SYS_NAND_MASK_ALE        (1 << 21)
 150/* our CLE is AD22 */
 151#define CONFIG_SYS_NAND_MASK_CLE        (1 << 22)
 152#define CONFIG_SYS_NAND_ENABLE_PIN      GPIO_PIN_PC(14)
 153#endif
 154
 155/* JFFS2 */
 156#ifdef CONFIG_CMD_JFFS2
 157#define CONFIG_MTD_NAND_ECC_JFFS2
 158#define CONFIG_JFFS2_CMDLINE
 159#define CONFIG_JFFS2_NAND
 160#endif
 161
 162/* Ethernet */
 163#define CONFIG_NET_RETRY_COUNT          20
 164#define CONFIG_MACB
 165#define CONFIG_RMII
 166#define CONFIG_PHY_ID                   0
 167#define CONFIG_MACB_SEARCH_PHY
 168
 169/* MMC */
 170#ifdef CONFIG_CMD_MMC
 171#define CONFIG_MMC
 172#define CONFIG_GENERIC_MMC
 173#define CONFIG_GENERIC_ATMEL_MCI
 174#define CONFIG_SYS_MMC_CD_PIN           AT91_PIO_PORTC, 8
 175#endif
 176
 177/* USB */
 178#ifdef CONFIG_CMD_USB
 179#define CONFIG_USB_ATMEL
 180#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
 181#define CONFIG_USB_OHCI_NEW
 182#define CONFIG_SYS_USB_OHCI_CPU_INIT
 183#define CONFIG_SYS_USB_OHCI_REGS_BASE   0x00500000
 184#define CONFIG_SYS_USB_OHCI_SLOT_NAME   "host"
 185#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      2
 186#define CONFIG_USB_STORAGE
 187#endif
 188
 189/* RTC */
 190#if defined(CONFIG_CMD_DATE) || defined(CONFIG_CMD_SNTP)
 191#define CONFIG_RTC_PCF8563
 192#define CONFIG_SYS_I2C_RTC_ADDR         0x51
 193#endif
 194
 195/* I2C */
 196#define CONFIG_SYS_MAX_I2C_BUS  1
 197
 198#define CONFIG_SYS_I2C
 199#define CONFIG_SYS_I2C_SOFT                     /* I2C bit-banged */
 200#define CONFIG_SYS_I2C_SOFT_SPEED       100000
 201#define CONFIG_SYS_I2C_SOFT_SLAVE       0
 202
 203#define I2C_SOFT_DECLARATIONS
 204
 205#define GPIO_I2C_SCL            AT91_PIO_PORTA, 24
 206#define GPIO_I2C_SDA            AT91_PIO_PORTA, 23
 207
 208#define I2C_INIT { \
 209        at91_set_pio_periph(AT91_PIO_PORTA, 23, 0); \
 210        at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
 211        at91_set_pio_periph(AT91_PIO_PORTA, 24, 0); \
 212        at91_set_pio_output(AT91_PIO_PORTA, 24, 0); \
 213        at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
 214}
 215
 216#define I2C_ACTIVE      at91_set_pio_output(AT91_PIO_PORTA, 23, 0)
 217#define I2C_TRISTATE    at91_set_pio_input(AT91_PIO_PORTA, 23, 0)
 218#define I2C_SCL(bit)    at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
 219#define I2C_SDA(bit)    at91_set_pio_value(AT91_PIO_PORTA, 23, bit)
 220#define I2C_DELAY       udelay(100)
 221#define I2C_READ        at91_get_pio_value(AT91_PIO_PORTA, 23)
 222
 223/* DHCP/BOOTP options */
 224#ifdef CONFIG_CMD_DHCP
 225#define CONFIG_BOOTP_BOOTFILESIZE
 226#define CONFIG_BOOTP_BOOTPATH
 227#define CONFIG_BOOTP_GATEWAY
 228#define CONFIG_BOOTP_HOSTNAME
 229#define CONFIG_SYS_AUTOLOAD     "n"
 230#endif
 231
 232/* File systems */
 233#define CONFIG_MTD_DEVICE
 234#define CONFIG_MTD_PARTITIONS
 235#if defined(CONFIG_CMD_MTDPARTS) || defined(CONFIG_CMD_NAND)
 236#define MTDIDS_DEFAULT          "nand0=atmel_nand"
 237#define MTDPARTS_DEFAULT        "mtdparts=atmel_nand:-(root)"
 238#endif
 239#if defined(CONFIG_CMD_REISER) || defined(CONFIG_CMD_EXT2) || \
 240        defined(CONFIG_CMD_USB) || defined(CONFIG_MMC)
 241#define CONFIG_DOS_PARTITION
 242#endif
 243#define CONFIG_LZO
 244#define CONFIG_RBTREE
 245
 246/* Boot command */
 247#define CONFIG_BOOTDELAY        3
 248#define CONFIG_CMDLINE_TAG
 249#define CONFIG_SETUP_MEMORY_TAGS
 250#define CONFIG_INITRD_TAG
 251#define CONFIG_BOOTCOMMAND      "cp.b 0xC00C6000 ${loadaddr} 0x294000; bootm"
 252#if defined(CONFIG_CMD_NAND)
 253#define CONFIG_BOOTARGS         "console=ttyS0,115200 " \
 254                                "root=/dev/mtdblock0 " \
 255                                MTDPARTS_DEFAULT \
 256                                " rw rootfstype=jffs2"
 257#endif
 258
 259/* Misc. u-boot settings */
 260#define CONFIG_SYS_PROMPT               "U-Boot> "
 261#define CONFIG_SYS_HUSH_PARSER
 262#define CONFIG_SYS_CBSIZE               256
 263#define CONFIG_SYS_MAXARGS              16
 264#define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + 16 \
 265                                        + sizeof(CONFIG_SYS_PROMPT))
 266#define CONFIG_SYS_LONGHELP
 267#define CONFIG_CMDLINE_EDITING
 268
 269#endif
 270