1/* 2 * Copyright (C) 2006 Bryan O'Donoghue, CodeHermit 3 * bodonoghue@codehermit.ie 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8#include <commproc.h> 9 10/* Mode Register */ 11#define USMOD_EN 0x01 12#define USMOD_HOST 0x02 13#define USMOD_TEST 0x04 14#define USMOD_SFTE 0x08 15#define USMOD_RESUME 0x40 16#define USMOD_LSS 0x80 17 18/* Endpoint Registers */ 19#define USEP_RHS_NORM 0x00 20#define USEP_RHS_IGNORE 0x01 21#define USEP_RHS_NAK 0x02 22#define USEP_RHS_STALL 0x03 23 24#define USEP_THS_NORM 0x00 25#define USEP_THS_IGNORE 0x04 26#define USEP_THS_NAK 0x08 27#define USEP_THS_STALL 0x0C 28 29#define USEP_RTE 0x10 30#define USEP_MF 0x20 31 32#define USEP_TM_CONTROL 0x00 33#define USEP_TM_INT 0x100 34#define USEP_TM_BULK 0x200 35#define USEP_TM_ISO 0x300 36 37/* Command Register */ 38#define USCOM_EP0 0x00 39#define USCOM_EP1 0x01 40#define USCOM_EP2 0x02 41#define USCOM_EP3 0x03 42 43#define USCOM_FLUSH 0x40 44#define USCOM_STR 0x80 45 46/* Event Register */ 47#define USB_E_RXB 0x0001 48#define USB_E_TXB 0x0002 49#define USB_E_BSY 0x0004 50#define USB_E_SOF 0x0008 51#define USB_E_TXE1 0x0010 52#define USB_E_TXE2 0x0020 53#define USB_E_TXE3 0x0040 54#define USB_E_TXE4 0x0080 55#define USB_TX_ERRMASK (USB_E_TXE1|USB_E_TXE2|USB_E_TXE3|USB_E_TXE4) 56#define USB_E_IDLE 0x0100 57#define USB_E_RESET 0x0200 58 59/* Mask Register */ 60#define USBS_IDLE 0x01 61 62/* RX Buffer Descriptor */ 63#define RX_BD_OV 0x02 64#define RX_BD_CR 0x04 65#define RX_BD_AB 0x08 66#define RX_BD_NO 0x10 67#define RX_BD_PID_DATA0 0x00 68#define RX_BD_PID_DATA1 0x40 69#define RX_BD_PID_SETUP 0x80 70#define RX_BD_F 0x400 71#define RX_BD_L 0x800 72#define RX_BD_I 0x1000 73#define RX_BD_W 0x2000 74#define RX_BD_E 0x8000 75 76/* Useful masks */ 77#define RX_BD_PID_BITMASK (RX_BD_PID_DATA1 | RX_BD_PID_SETUP) 78#define STALL_BITMASK (USEP_THS_STALL | USEP_RHS_STALL) 79#define NAK_BITMASK (USEP_THS_NAK | USEP_RHS_NAK) 80#define CBD_TX_BITMASK (TX_BD_R | TX_BD_L | TX_BD_TC | TX_BD_I | TX_BD_CNF) 81 82/* TX Buffer Descriptor */ 83#define TX_BD_UN 0x02 84#define TX_BD_TO 0x04 85#define TX_BD_NO_PID 0x00 86#define TX_BD_PID_DATA0 0x80 87#define TX_BD_PID_DATA1 0xC0 88#define TX_BD_CNF 0x200 89#define TX_BD_TC 0x400 90#define TX_BD_L 0x800 91#define TX_BD_I 0x1000 92#define TX_BD_W 0x2000 93#define TX_BD_R 0x8000 94 95/* Implementation specific defines */ 96 97#define EP_MIN_PACKET_SIZE 0x08 98#define MAX_ENDPOINTS 0x04 99#define FIFO_SIZE 0x10 100#define EP_MAX_PKT FIFO_SIZE 101#define TX_RING_SIZE 0x04 102#define RX_RING_SIZE 0x06 103#define USB_MAX_PKT 0x40 104#define TOGGLE_TX_PID(x) x= ((~x)&0x40)|0x80 105#define TOGGLE_RX_PID(x) x^= 0x40 106#define EP_ATTACHED 0x01 /* Endpoint has a urb attached or not */ 107#define EP_SEND_ZLP 0x02 /* Send ZLP y/n ? */ 108 109#define PROFF_USB 0x00000000 110#define CPM_USB_BASE 0x00000A00 111 112/* UDC device defines */ 113#define EP0_MAX_PACKET_SIZE EP_MAX_PKT 114 115#define UDC_OUT_PACKET_SIZE EP_MIN_PACKET_SIZE 116#define UDC_IN_PACKET_SIZE EP_MIN_PACKET_SIZE 117#define UDC_INT_PACKET_SIZE UDC_IN_PACKET_SIZE 118#define UDC_BULK_PACKET_SIZE EP_MIN_PACKET_SIZE 119 120struct mpc8xx_ep { 121 struct urb * urb; 122 unsigned char pid; 123 unsigned char sc; 124 volatile cbd_t * prx; 125}; 126 127typedef struct mpc8xx_usb{ 128 char usmod; /* Mode Register */ 129 char usaddr; /* Slave Address Register */ 130 char uscom; /* Command Register */ 131 char res1; /* Reserved */ 132 ushort usep[4]; 133 ulong res2; /* Reserved */ 134 ushort usber; /* Event Register */ 135 ushort res3; /* Reserved */ 136 ushort usbmr; /* Mask Register */ 137 char res4; /* Reserved */ 138 char usbs; /* Status Register */ 139 char res5[8]; /* Reserved */ 140}usb_t; 141 142typedef struct mpc8xx_parameter_ram{ 143 ushort ep0ptr; /* Endpoint Pointer Register 0 */ 144 ushort ep1ptr; /* Endpoint Pointer Register 1 */ 145 ushort ep2ptr; /* Endpoint Pointer Register 2 */ 146 ushort ep3ptr; /* Endpoint Pointer Register 3 */ 147 uint rstate; /* Receive state */ 148 uint rptr; /* Receive internal data pointer */ 149 ushort frame_n; /* Frame number */ 150 ushort rbcnt; /* Receive byte count */ 151 uint rtemp; /* Receive temp cp use only */ 152 uint rxusb; /* Rx Data Temp */ 153 ushort rxuptr; /* Rx microcode return address temp */ 154}usb_pram_t; 155 156typedef struct endpoint_parameter_block_pointer{ 157 ushort rbase; /* RxBD base address */ 158 ushort tbase; /* TxBD base address */ 159 char rfcr; /* Rx Function code */ 160 char tfcr; /* Tx Function code */ 161 ushort mrblr; /* Maximum Receive Buffer Length */ 162 ushort rbptr; /* RxBD pointer Next Buffer Descriptor */ 163 ushort tbptr; /* TxBD pointer Next Buffer Descriptor */ 164 ulong tstate; /* Transmit internal state */ 165 ulong tptr; /* Transmit internal data pointer */ 166 ushort tcrc; /* Transmit temp CRC */ 167 ushort tbcnt; /* Transmit internal bye count */ 168 ulong ttemp; /* Tx temp */ 169 ushort txuptr; /* Tx microcode return address */ 170 ushort res1; /* Reserved */ 171}usb_epb_t; 172 173typedef enum mpc8xx_udc_state{ 174 STATE_NOT_READY, 175 STATE_ERROR, 176 STATE_READY, 177}mpc8xx_udc_state_t; 178 179