1
2
3
4
5
6
7
8
9
10
11
12#include <common.h>
13#include <config.h>
14#include <asm/blackfin.h>
15#include <asm/io.h>
16#include <asm/dma.h>
17
18char *strcpy(char *dest, const char *src)
19{
20 char *xdest = dest;
21 char temp = 0;
22
23 __asm__ __volatile__ (
24 "1:\t%2 = B [%1++] (Z);\n\t"
25 "B [%0++] = %2;\n\t"
26 "CC = %2;\n\t"
27 "if cc jump 1b (bp);\n"
28 : "=a"(dest), "=a"(src), "=d"(temp)
29 : "0"(dest), "1"(src), "2"(temp)
30 : "memory");
31
32 return xdest;
33}
34
35char *strncpy(char *dest, const char *src, size_t n)
36{
37 char *xdest = dest;
38 char temp = 0;
39
40 if (n == 0)
41 return xdest;
42
43 __asm__ __volatile__ (
44 "1:\t%3 = B [%1++] (Z);\n\t"
45 "B [%0++] = %3;\n\t"
46 "CC = %3;\n\t"
47 "if ! cc jump 2f;\n\t"
48 "%2 += -1;\n\t"
49 "CC = %2 == 0;\n\t"
50 "if ! cc jump 1b (bp);\n"
51 "2:\n"
52 : "=a"(dest), "=a"(src), "=da"(n), "=d"(temp)
53 : "0"(dest), "1"(src), "2"(n), "3"(temp)
54 : "memory");
55
56 return xdest;
57}
58
59int strcmp(const char *cs, const char *ct)
60{
61 char __res1, __res2;
62
63 __asm__ (
64 "1:\t%2 = B[%0++] (Z);\n\t"
65 "%3 = B[%1++] (Z);\n\t"
66 "CC = %2 == %3;\n\t"
67 "if ! cc jump 2f;\n\t"
68 "CC = %2;\n\t"
69 "if cc jump 1b (bp);\n\t"
70 "jump.s 3f;\n"
71 "2:\t%2 = %2 - %3;\n"
72 "3:\n"
73 : "=a"(cs), "=a"(ct), "=d"(__res1), "=d"(__res2)
74 : "0"(cs), "1"(ct));
75
76 return __res1;
77}
78
79int strncmp(const char *cs, const char *ct, size_t count)
80{
81 char __res1, __res2;
82
83 if (!count)
84 return 0;
85
86 __asm__(
87 "1:\t%3 = B[%0++] (Z);\n\t"
88 "%4 = B[%1++] (Z);\n\t"
89 "CC = %3 == %4;\n\t"
90 "if ! cc jump 3f;\n\t"
91 "CC = %3;\n\t"
92 "if ! cc jump 4f;\n\t"
93 "%2 += -1;\n\t"
94 "CC = %2 == 0;\n\t" "if ! cc jump 1b;\n"
95 "2:\t%3 = 0;\n\t"
96 "jump.s 4f;\n" "3:\t%3 = %3 - %4;\n"
97 "4:"
98 : "=a"(cs), "=a"(ct), "=da"(count), "=d"(__res1), "=d"(__res2)
99 : "0"(cs), "1"(ct), "2"(count));
100
101 return __res1;
102}
103
104#ifdef MDMA1_D0_NEXT_DESC_PTR
105# define MDMA_D0_NEXT_DESC_PTR MDMA1_D0_NEXT_DESC_PTR
106# define MDMA_S0_NEXT_DESC_PTR MDMA1_S0_NEXT_DESC_PTR
107#endif
108
109static void dma_calc_size(unsigned long ldst, unsigned long lsrc, size_t count,
110 unsigned long *dshift, unsigned long *bpos)
111{
112 unsigned long limit;
113
114#ifdef MSIZE
115
116 limit = 5;
117 *dshift = MSIZE_P;
118#else
119
120 limit = 2;
121 *dshift = WDSIZE_P;
122#endif
123
124 *bpos = min(limit, ffs(ldst | lsrc | count)) - 1;
125}
126
127
128
129
130
131void dma_memcpy_nocache(void *dst, const void *src, size_t count)
132{
133 struct dma_register *mdma_d0 = (void *)MDMA_D0_NEXT_DESC_PTR;
134 struct dma_register *mdma_s0 = (void *)MDMA_S0_NEXT_DESC_PTR;
135 unsigned long ldst = (unsigned long)dst;
136 unsigned long lsrc = (unsigned long)src;
137 unsigned long dshift, bpos;
138 uint32_t dsize, mod;
139
140
141
142
143
144 bfin_write(&mdma_d0->config, 0);
145 bfin_write(&mdma_s0->config, 0);
146 bfin_write(&mdma_d0->status, DMA_RUN | DMA_DONE | DMA_ERR);
147
148
149 if ((lsrc >= L1_SRAM_SCRATCH && lsrc < L1_SRAM_SCRATCH_END) ||
150 (ldst >= L1_SRAM_SCRATCH && ldst < L1_SRAM_SCRATCH_END))
151 hang();
152
153 dma_calc_size(ldst, lsrc, count, &dshift, &bpos);
154 dsize = bpos << dshift;
155 count >>= bpos;
156 mod = 1 << bpos;
157
158#ifdef PSIZE
159
160 dsize |= min(2, bpos) << PSIZE_P;
161#endif
162
163
164
165 bfin_write(&mdma_d0->start_addr, ldst);
166
167 bfin_write(&mdma_d0->x_count, count);
168
169 bfin_write(&mdma_d0->x_modify, mod);
170
171
172 bfin_write(&mdma_s0->start_addr, lsrc);
173
174 bfin_write(&mdma_s0->x_count, count);
175
176 bfin_write(&mdma_s0->x_modify, mod);
177
178
179 bfin_write(&mdma_s0->config, dsize | DMAEN);
180 bfin_write(&mdma_d0->config, dsize | DMAEN | WNR | DI_EN);
181 SSYNC();
182
183 while (!(bfin_read(&mdma_d0->status) & DMA_DONE))
184 continue;
185
186 bfin_write(&mdma_d0->status, DMA_RUN | DMA_DONE | DMA_ERR);
187 bfin_write(&mdma_d0->config, 0);
188 bfin_write(&mdma_s0->config, 0);
189}
190
191
192
193
194void *dma_memcpy(void *dst, const void *src, size_t count)
195{
196 if (dcache_status()) {
197 blackfin_dcache_flush_range(src, src + count);
198 blackfin_dcache_flush_invalidate_range(dst, dst + count);
199 }
200
201 dma_memcpy_nocache(dst, src, count);
202
203 if (icache_status())
204 blackfin_icache_flush_range(dst, dst + count);
205
206 return dst;
207}
208
209
210
211
212
213
214
215
216
217
218
219
220
221extern void *memcpy_ASM(void *dst, const void *src, size_t count);
222void *memcpy(void *dst, const void *src, size_t count)
223{
224 if (!count)
225 return dst;
226
227#ifdef CONFIG_CMD_KGDB
228 if (src >= (void *)SYSMMR_BASE) {
229 if (count == 2 && (unsigned long)src % 2 == 0) {
230 u16 mmr = bfin_read16(src);
231 memcpy(dst, &mmr, sizeof(mmr));
232 return dst;
233 }
234 if (count == 4 && (unsigned long)src % 4 == 0) {
235 u32 mmr = bfin_read32(src);
236 memcpy(dst, &mmr, sizeof(mmr));
237 return dst;
238 }
239
240 memset(dst, 0xad, count);
241 return dst;
242 }
243 if (dst >= (void *)SYSMMR_BASE) {
244 if (count == 2 && (unsigned long)dst % 2 == 0) {
245 u16 mmr;
246 memcpy(&mmr, src, sizeof(mmr));
247 bfin_write16(dst, mmr);
248 return dst;
249 }
250 if (count == 4 && (unsigned long)dst % 4 == 0) {
251 u32 mmr;
252 memcpy(&mmr, src, sizeof(mmr));
253 bfin_write32(dst, mmr);
254 return dst;
255 }
256
257 memset(dst, 0xad, count);
258 return dst;
259 }
260#endif
261
262
263 if (addr_bfin_on_chip_mem(dst) || addr_bfin_on_chip_mem(src))
264 return dma_memcpy(dst, src, count);
265 else
266
267 return memcpy_ASM(dst, src, count);
268}
269