LXR uboot/board/csb272/csb272.c

   1/*
   2 * (C) Copyright 2004
   3 * Tolunay Orkun, Nextio Inc., torkun@nextio.com
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8#include <common.h>
   9#include <asm/processor.h>
  10#include <i2c.h>
  11#include <miiphy.h>
  12#include <asm/ppc4xx-emac.h>
  13
  14void sdram_init(void);
  15
  16/*
  17 * Configuration data for AMIS FS6377-01 Programmable 3-PLL Clock Generator
  18 *
  19 * CLKA output => Epson LCD Controller
  20 * CLKB output => Not Connected
  21 * CLKC output => Ethernet
  22 * CLKD output => UART external clock
  23 *
  24 * Note: these values are obtained from device after init by micromonitor
  25*/
  26uchar pll_fs6377_regs[16] = {
  27        0x28, 0xef, 0x53, 0x03, 0x4b, 0x80, 0x32, 0x80,
  28        0x94, 0x32, 0x80, 0xd4, 0x56, 0xf6, 0xf6, 0xe0 };
  29
  30/*
  31 * pll_init: Initialize AMIS IC FS6377-01 PLL
  32 *
  33 * PLL supplies Epson LCD Clock, Ethernet Clock and UART external clock
  34 *
  35 */
  36int pll_init(void)
  37{
  38        i2c_set_bus_num(0);
  39
  40        return  i2c_write(CONFIG_SYS_I2C_PLL_ADDR, 0, 1,
  41                (uchar *) pll_fs6377_regs, sizeof(pll_fs6377_regs));
  42}
  43
  44/*
  45 * board_early_init_f: do early board initialization
  46 *
  47 */
  48int board_early_init_f(void)
  49{
  50        /* initialize PLL so UART, LCD, Ethernet clocked at correctly */
  51        (void) get_clocks();
  52        pll_init();
  53
  54   /*-------------------------------------------------------------------------+
  55   | Interrupt controller setup for the Walnut board.
  56   | Note: IRQ 0-15  405GP internally generated; active high; level sensitive
  57   |       IRQ 16    405GP internally generated; active low; level sensitive
  58   |       IRQ 17-24 RESERVED
  59   |       IRQ 25 (EXT IRQ 0) FPGA; active high; level sensitive
  60   |       IRQ 26 (EXT IRQ 1) SMI; active high; level sensitive
  61   |       IRQ 27 (EXT IRQ 2) Not Used
  62   |       IRQ 28 (EXT IRQ 3) PCI SLOT 3; active low; level sensitive
  63   |       IRQ 29 (EXT IRQ 4) PCI SLOT 2; active low; level sensitive
  64   |       IRQ 30 (EXT IRQ 5) PCI SLOT 1; active low; level sensitive
  65   |       IRQ 31 (EXT IRQ 6) PCI SLOT 0; active low; level sensitive
  66   | Note for Walnut board:
  67   |       An interrupt taken for the FPGA (IRQ 25) indicates that either
  68   |       the Mouse, Keyboard, IRDA, or External Expansion caused the
  69   |       interrupt. The FPGA must be read to determine which device
  70   |       caused the interrupt. The default setting of the FPGA clears
  71   |
  72   +-------------------------------------------------------------------------*/
  73
  74        mtdcr (UIC0SR, 0xFFFFFFFF);   /* clear all ints */
  75        mtdcr (UIC0ER, 0x00000000);   /* disable all ints */
  76        mtdcr (UIC0CR, 0x00000000);   /* set all to be non-critical */
  77        mtdcr (UIC0PR, 0xFFFFFF83);   /* set int polarities */
  78        mtdcr (UIC0TR, 0x10000000);   /* set int trigger levels */
  79        mtdcr (UIC0VCR, 0x00000001);  /* set vect base=0,INT0 highest priority */
  80        mtdcr (UIC0SR, 0xFFFFFFFF);   /* clear all ints */
  81
  82        mtebc (EBC0_CFG, 0xa8400000);   /* EBC always driven */
  83
  84        return 0; /* success */
  85}
  86
  87/*
  88 * checkboard: identify/verify the board we are running
  89 *
  90 * Remark: we just assume it is correct board here!
  91 *
  92 */
  93int checkboard(void)
  94{
  95        printf("BOARD: Cogent CSB272\n");
  96
  97        return 0; /* success */
  98}
  99
 100/*
 101 * initram: Determine the size of mounted DRAM
 102 *
 103 * Size is determined by reading SDRAM configuration registers as
 104 * configured by initialization code
 105 *
 106 */
 107phys_size_t initdram (int board_type)
 108{
 109        ulong tot_size;
 110        ulong bank_size;
 111        ulong tmp;
 112
 113        /*
 114         * ToDo: Move the asm init routine sdram_init() to this C file,
 115         * or even better use some common ppc4xx code available
 116         * in arch/powerpc/cpu/ppc4xx
 117         */
 118        sdram_init();
 119
 120        tot_size = 0;
 121
 122        mtdcr (SDRAM0_CFGADDR, SDRAM0_B0CR);
 123        tmp = mfdcr (SDRAM0_CFGDATA);
 124        if (tmp & 0x00000001) {
 125                bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
 126                tot_size += bank_size;
 127        }
 128
 129        mtdcr (SDRAM0_CFGADDR, SDRAM0_B1CR);
 130        tmp = mfdcr (SDRAM0_CFGDATA);
 131        if (tmp & 0x00000001) {
 132                bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
 133                tot_size += bank_size;
 134        }
 135
 136        mtdcr (SDRAM0_CFGADDR, SDRAM0_B2CR);
 137        tmp = mfdcr (SDRAM0_CFGDATA);
 138        if (tmp & 0x00000001) {
 139                bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
 140                tot_size += bank_size;
 141        }
 142
 143        mtdcr (SDRAM0_CFGADDR, SDRAM0_B3CR);
 144        tmp = mfdcr (SDRAM0_CFGDATA);
 145        if (tmp & 0x00000001) {
 146                bank_size = 0x00400000 << ((tmp >> 17) & 0x7);
 147                tot_size += bank_size;
 148        }
 149
 150        return tot_size;
 151}
 152
 153/*
 154 * last_stage_init: final configurations (such as PHY etc)
 155 *
 156 */
 157int last_stage_init(void)
 158{
 159        /* initialize the PHY */
 160        miiphy_reset("ppc_4xx_eth0", CONFIG_PHY_ADDR);
 161
 162        /* AUTO neg */
 163        miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_BMCR,
 164                        BMCR_ANENABLE | BMCR_ANRESTART);
 165
 166        /* LEDs     */
 167        miiphy_write("ppc_4xx_eth0", CONFIG_PHY_ADDR, MII_NWAYTEST, 0x0d08);
 168
 169
 170        return 0; /* success */
 171}
 172