LXR uboot/board/esd/cpci750/sdram

   1/*
   2 * (C) Copyright 2001
   3 * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8/*************************************************************************
   9 * adaption for the Marvell DB64360 Board
  10 * Ingo Assmus (ingo.assmus@keymile.com)
  11 *
  12 * adaption for the cpci750 Board
  13 * Reinhard Arlt (reinhard.arlt@esd-electronics.com)
  14 *************************************************************************/
  15
  16
  17/* sdram_init.c - automatic memory sizing */
  18
  19#include <common.h>
  20#include <74xx_7xx.h>
  21#include "../../Marvell/include/memory.h"
  22#include "../../Marvell/include/pci.h"
  23#include "../../Marvell/include/mv_gen_reg.h"
  24#include <net.h>
  25
  26#include "eth.h"
  27#include "mpsc.h"
  28#include "../../Marvell/common/i2c.h"
  29#include "64360.h"
  30#include "mv_regs.h"
  31
  32DECLARE_GLOBAL_DATA_PTR;
  33
  34int set_dfcdlInit(void);        /* setup delay line of Mv64360 */
  35
  36/* ------------------------------------------------------------------------- */
  37
  38int
  39memory_map_bank(unsigned int bankNo,
  40                unsigned int bankBase,
  41                unsigned int bankLength)
  42{
  43#ifdef MAP_PCI
  44        PCI_HOST host;
  45#endif
  46
  47
  48#ifdef DEBUG
  49        if (bankLength > 0) {
  50                printf("mapping bank %d at %08x - %08x\n",
  51                       bankNo, bankBase, bankBase + bankLength - 1);
  52        } else {
  53                printf("unmapping bank %d\n", bankNo);
  54        }
  55#endif
  56
  57        memoryMapBank(bankNo, bankBase, bankLength);
  58
  59#ifdef MAP_PCI
  60        for (host=PCI_HOST0;host<=PCI_HOST1;host++) {
  61                const int features=
  62                        PREFETCH_ENABLE |
  63                        DELAYED_READ_ENABLE |
  64                        AGGRESSIVE_PREFETCH |
  65                        READ_LINE_AGGRESSIVE_PREFETCH |
  66                        READ_MULTI_AGGRESSIVE_PREFETCH |
  67                        MAX_BURST_4 |
  68                        PCI_NO_SWAP;
  69
  70                pciMapMemoryBank(host, bankNo, bankBase, bankLength);
  71
  72                pciSetRegionSnoopMode(host, bankNo, PCI_SNOOP_WB, bankBase,
  73                                bankLength);
  74
  75                pciSetRegionFeatures(host, bankNo, features, bankBase, bankLength);
  76        }
  77#endif
  78        return 0;
  79}
  80
  81#define GB         (1 << 30)
  82
  83/* much of this code is based on (or is) the code in the pip405 port */
  84/* thanks go to the authors of said port - Josh */
  85
  86/* structure to store the relevant information about an sdram bank */
  87typedef struct sdram_info {
  88        uchar drb_size;
  89        uchar registered, ecc;
  90        uchar tpar;
  91        uchar tras_clocks;
  92        uchar burst_len;
  93        uchar banks, slot;
  94} sdram_info_t;
  95
  96/* Typedefs for 'gtAuxilGetDIMMinfo' function */
  97
  98typedef enum _memoryType {SDRAM, DDR} MEMORY_TYPE;
  99
 100typedef enum _voltageInterface {TTL_5V_TOLERANT, LVTTL, HSTL_1_5V,
 101                                SSTL_3_3V, SSTL_2_5V, VOLTAGE_UNKNOWN,
 102                               } VOLTAGE_INTERFACE;
 103
 104typedef enum _max_CL_supported_DDR {DDR_CL_1=1, DDR_CL_1_5=2, DDR_CL_2=4, DDR_CL_2_5=8, DDR_CL_3=16, DDR_CL_3_5=32, DDR_CL_FAULT} MAX_CL_SUPPORTED_DDR;
 105typedef enum _max_CL_supported_SD {SD_CL_1=1,  SD_CL_2,  SD_CL_3, SD_CL_4, SD_CL_5, SD_CL_6, SD_CL_7, SD_FAULT} MAX_CL_SUPPORTED_SD;
 106
 107
 108/* SDRAM/DDR information struct */
 109typedef struct _gtMemoryDimmInfo {
 110        MEMORY_TYPE memoryType;
 111        unsigned int numOfRowAddresses;
 112        unsigned int numOfColAddresses;
 113        unsigned int numOfModuleBanks;
 114        unsigned int dataWidth;
 115        VOLTAGE_INTERFACE voltageInterface;
 116        unsigned int errorCheckType;                    /* ECC , PARITY.. */
 117        unsigned int sdramWidth;                        /* 4,8,16 or 32 */ ;
 118        unsigned int errorCheckDataWidth;               /* 0 - no, 1 - Yes */
 119        unsigned int minClkDelay;
 120        unsigned int burstLengthSupported;
 121        unsigned int numOfBanksOnEachDevice;
 122        unsigned int suportedCasLatencies;
 123        unsigned int RefreshInterval;
 124        unsigned int maxCASlatencySupported_LoP;        /* LoP left of point (measured in ns) */
 125        unsigned int maxCASlatencySupported_RoP;        /* RoP right of point (measured in ns) */
 126        MAX_CL_SUPPORTED_DDR maxClSupported_DDR;
 127        MAX_CL_SUPPORTED_SD maxClSupported_SD;
 128        unsigned int moduleBankDensity;
 129        /* module attributes (true for yes) */
 130        bool bufferedAddrAndControlInputs;
 131        bool registeredAddrAndControlInputs;
 132        bool onCardPLL;
 133        bool bufferedDQMBinputs;
 134        bool registeredDQMBinputs;
 135        bool differentialClockInput;
 136        bool redundantRowAddressing;
 137
 138        /* module general attributes */
 139        bool suportedAutoPreCharge;
 140        bool suportedPreChargeAll;
 141        bool suportedEarlyRasPreCharge;
 142        bool suportedWrite1ReadBurst;
 143        bool suported5PercentLowVCC;
 144        bool suported5PercentUpperVCC;
 145        /* module timing parameters */
 146        unsigned int minRasToCasDelay;
 147        unsigned int minRowActiveRowActiveDelay;
 148        unsigned int minRasPulseWidth;
 149        unsigned int minRowPrechargeTime;               /* measured in ns */
 150
 151        int addrAndCommandHoldTime;                     /* LoP left of point (measured in ns) */
 152        int addrAndCommandSetupTime;                    /* (measured in ns/100) */
 153        int dataInputSetupTime;                         /* LoP left of point (measured in ns) */
 154        int dataInputHoldTime;                          /* LoP left of point (measured in ns) */
 155/* tAC times for highest 2nd and 3rd highest CAS Latency values */
 156        unsigned int clockToDataOut_LoP;                /* LoP left of point (measured in ns) */
 157        unsigned int clockToDataOut_RoP;                /* RoP right of point (measured in ns) */
 158        unsigned int clockToDataOutMinus1_LoP;          /* LoP left of point (measured in ns) */
 159        unsigned int clockToDataOutMinus1_RoP;          /* RoP right of point (measured in ns) */
 160        unsigned int clockToDataOutMinus2_LoP;          /* LoP left of point (measured in ns) */
 161        unsigned int clockToDataOutMinus2_RoP;          /* RoP right of point (measured in ns) */
 162
 163        unsigned int minimumCycleTimeAtMaxCasLatancy_LoP;       /* LoP left of point (measured in ns) */
 164        unsigned int minimumCycleTimeAtMaxCasLatancy_RoP;       /* RoP right of point (measured in ns) */
 165
 166        unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_LoP; /* LoP left of point (measured in ns) */
 167        unsigned int minimumCycleTimeAtMaxCasLatancyMinus1_RoP; /* RoP right of point (measured in ns) */
 168
 169        unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_LoP; /* LoP left of point (measured in ns) */
 170        unsigned int minimumCycleTimeAtMaxCasLatancyMinus2_RoP; /* RoP right of point (measured in ns) */
 171
 172        /* Parameters calculated from
 173           the extracted DIMM information */
 174        unsigned int size;
 175        unsigned int deviceDensity;                     /* 16,64,128,256 or 512 Mbit */
 176        unsigned int numberOfDevices;
 177        uchar drb_size;                                 /* DRAM size in n*64Mbit */
 178        uchar slot;                                     /* Slot Number this module is inserted in */
 179        uchar spd_raw_data[128];                        /* Content of SPD-EEPROM copied 1:1 */
 180#ifdef DEBUG
 181        uchar manufactura[8];                           /* Content of SPD-EEPROM Byte 64-71 */
 182        uchar modul_id[18];                             /* Content of SPD-EEPROM Byte 73-90 */
 183        uchar vendor_data[27];                          /* Content of SPD-EEPROM Byte 99-125 */
 184        unsigned long modul_serial_no;                  /* Content of SPD-EEPROM Byte 95-98 */
 185        unsigned int manufac_date;                      /* Content of SPD-EEPROM Byte 93-94 */
 186        unsigned int modul_revision;                    /* Content of SPD-EEPROM Byte 91-92 */
 187        uchar manufac_place;                            /* Content of SPD-EEPROM Byte 72 */
 188
 189#endif
 190} AUX_MEM_DIMM_INFO;
 191
 192
 193/*
 194 * translate ns.ns/10 coding of SPD timing values
 195 * into 10 ps unit values
 196 */
 197static inline unsigned short
 198NS10to10PS(unsigned char spd_byte)
 199{
 200        unsigned short ns, ns10;
 201
 202        /* isolate upper nibble */
 203        ns = (spd_byte >> 4) & 0x0F;
 204        /* isolate lower nibble */
 205        ns10 = (spd_byte & 0x0F);
 206
 207        return(ns*100 + ns10*10);
 208}
 209
 210/*
 211 * translate ns coding of SPD timing values
 212 * into 10 ps unit values
 213 */
 214static inline unsigned short
 215NSto10PS(unsigned char spd_byte)
 216{
 217        return(spd_byte*100);
 218}
 219
 220/* This code reads the SPD chip on the sdram and populates
 221 * the array which is passed in with the relevant information */
 222/* static int check_dimm(uchar slot, AUX_MEM_DIMM_INFO *info) */
 223static int check_dimm (uchar slot, AUX_MEM_DIMM_INFO * dimmInfo)
 224{
 225        uchar addr = slot == 0 ? DIMM0_I2C_ADDR : DIMM1_I2C_ADDR;
 226        int ret;
 227        unsigned int i, j, density = 1, devicesForErrCheck = 0;
 228
 229#ifdef DEBUG
 230        unsigned int k;
 231#endif
 232        unsigned int rightOfPoint = 0, leftOfPoint = 0, mult, div, time_tmp;
 233        int sign = 1, shift, maskLeftOfPoint, maskRightOfPoint;
 234        uchar supp_cal, cal_val;
 235        ulong memclk, tmemclk;
 236        ulong tmp;
 237        uchar trp_clocks = 0, tras_clocks;
 238        uchar data[128];
 239
 240        memclk = gd->bus_clk;
 241        tmemclk = 1000000000 / (memclk / 100);  /* in 10 ps units */
 242
 243        memset (data, 0, sizeof (data));
 244
 245
 246        ret = 0;
 247
 248        debug("before i2c read\n");
 249
 250        ret = i2c_read (addr, 0, 2, data, 128);
 251
 252        debug("after i2c read\n");
 253
 254        if ((data[64] != 'e') || (data[65] != 's') || (data[66] != 'd')
 255            || (data[67] != '-') || (data[68] != 'g') || (data[69] != 'm')
 256            || (data[70] != 'b') || (data[71] != 'h')) {
 257                ret = -1;
 258        }
 259
 260        if ((ret != 0) && (slot == 0)) {
 261                memset (data, 0, sizeof (data));
 262                data[0] = 0x80;
 263                data[1] = 0x08;
 264                data[2] = 0x07;
 265                data[3] = 0x0c;
 266                data[4] = 0x09;
 267                data[5] = 0x01;
 268                data[6] = 0x48;
 269                data[7] = 0x00;
 270                data[8] = 0x04;
 271                data[9] = 0x75;
 272                data[10] = 0x80;
 273                data[11] = 0x02;
 274                data[12] = 0x80;
 275                data[13] = 0x10;
 276                data[14] = 0x08;
 277                data[15] = 0x01;
 278                data[16] = 0x0e;
 279                data[17] = 0x04;
 280                data[18] = 0x0c;
 281                data[19] = 0x01;
 282                data[20] = 0x02;
 283                data[21] = 0x20;
 284                data[22] = 0x00;
 285                data[23] = 0xa0;
 286                data[24] = 0x80;
 287                data[25] = 0x00;
 288                data[26] = 0x00;
 289                data[27] = 0x50;
 290                data[28] = 0x3c;
 291                data[29] = 0x50;
 292                data[30] = 0x32;
 293                data[31] = 0x10;
 294                data[32] = 0xb0;
 295                data[33] = 0xb0;
 296                data[34] = 0x60;
 297                data[35] = 0x60;
 298                data[64] = 'e';
 299                data[65] = 's';
 300                data[66] = 'd';
 301                data[67] = '-';
 302                data[68] = 'g';
 303                data[69] = 'm';
 304                data[70] = 'b';
 305                data[71] = 'h';
 306                ret = 0;
 307        }
 308
 309        /* zero all the values */
 310        memset (dimmInfo, 0, sizeof (*dimmInfo));
 311
 312        /* copy the SPD content 1:1 into the dimmInfo structure */
 313        for (i = 0; i <= 127; i++) {
 314                dimmInfo->spd_raw_data[i] = data[i];
 315        }
 316
 317        if (ret) {
 318                debug("No DIMM in slot %d [err = %x]\n", slot, ret);
 319                return 0;
 320        } else
 321                dimmInfo->slot = slot;  /* start to fill up dimminfo for this "slot" */
 322
 323#ifdef CONFIG_SYS_DISPLAY_DIMM_SPD_CONTENT
 324
 325        for (i = 0; i <= 127; i++) {
 326                printf ("SPD-EEPROM Byte %3d = %3x (%3d)\n", i, data[i],
 327                        data[i]);
 328        }
 329
 330#endif
 331#ifdef DEBUG
 332        /* find Manufacturer of Dimm Module */
 333        for (i = 0; i < sizeof (dimmInfo->manufactura); i++) {
 334                dimmInfo->manufactura[i] = data[64 + i];
 335        }
 336        printf ("\nThis RAM-Module is produced by:              %s\n",
 337                dimmInfo->manufactura);
 338
 339        /* find Manul-ID of Dimm Module */
 340        for (i = 0; i < sizeof (dimmInfo->modul_id); i++) {
 341                dimmInfo->modul_id[i] = data[73 + i];
 342        }
 343        printf ("The Module-ID of this RAM-Module is:           %s\n",
 344                dimmInfo->modul_id);
 345
 346        /* find Vendor-Data of Dimm Module */
 347        for (i = 0; i < sizeof (dimmInfo->vendor_data); i++) {
 348                dimmInfo->vendor_data[i] = data[99 + i];
 349        }
 350        printf ("Vendor Data of this RAM-Module is:             %s\n",
 351                dimmInfo->vendor_data);
 352
 353        /* find modul_serial_no of Dimm Module */
 354        dimmInfo->modul_serial_no = (*((unsigned long *) (&data[95])));
 355        printf ("Serial No. of this RAM-Module is:              %ld (%lx)\n",
 356                dimmInfo->modul_serial_no, dimmInfo->modul_serial_no);
 357
 358        /* find Manufac-Data of Dimm Module */
 359        dimmInfo->manufac_date = (*((unsigned int *) (&data[93])));
 360        printf ("Manufactoring Date of this RAM-Module is:      %d.%d\n", data[93], data[94]);  /*dimmInfo->manufac_date */
 361
 362        /* find modul_revision of Dimm Module */
 363        dimmInfo->modul_revision = (*((unsigned int *) (&data[91])));
 364        printf ("Module Revision of this RAM-Module is:                 %d.%d\n", data[91], data[92]);  /* dimmInfo->modul_revision */
 365
 366        /* find manufac_place of Dimm Module */
 367        dimmInfo->manufac_place = (*((unsigned char *) (&data[72])));
 368        printf ("manufac_place of this RAM-Module is:           %d\n",
 369                dimmInfo->manufac_place);
 370
 371#endif
 372/*------------------------------------------------------------------------------------------------------------------------------*/
 373/* calculate SPD checksum */
 374/*------------------------------------------------------------------------------------------------------------------------------*/
 375#if 0                           /* test-only */
 376        spd_checksum = 0;
 377
 378        for (i = 0; i <= 62; i++) {
 379                spd_checksum += data[i];
 380        }
 381
 382        if ((spd_checksum & 0xff) != data[63]) {
 383                printf ("### Error in SPD Checksum !!! Is_value: %2x should value %2x\n", (unsigned int) (spd_checksum & 0xff), data[63]);
 384                hang ();
 385        }
 386
 387        else
 388                printf ("SPD Checksum ok!\n");
 389#endif /* test-only */
 390
 391/*------------------------------------------------------------------------------------------------------------------------------*/
 392        for (i = 2; i <= 35; i++) {
 393                switch (i) {
 394                case 2: /* Memory type (DDR / SDRAM) */
 395                        dimmInfo->memoryType = (data[i] == 0x7) ? DDR : SDRAM;
 396#ifdef DEBUG
 397                        if (dimmInfo->memoryType == 0)
 398                                debug("Dram_type in slot %d is:                 SDRAM\n",
 399                                     dimmInfo->slot);
 400                        if (dimmInfo->memoryType == 1)
 401                                debug("Dram_type in slot %d is:                 DDRAM\n",
 402                                     dimmInfo->slot);
 403#endif
 404                        break;
 405/*------------------------------------------------------------------------------------------------------------------------------*/
 406
 407                case 3: /* Number Of Row Addresses */
 408                        dimmInfo->numOfRowAddresses = data[i];
 409                        debug("Module Number of row addresses:          %d\n",
 410                             dimmInfo->numOfRowAddresses);
 411                        break;
 412/*------------------------------------------------------------------------------------------------------------------------------*/
 413
 414                case 4: /* Number Of Column Addresses */
 415                        dimmInfo->numOfColAddresses = data[i];
 416                        debug("Module Number of col addresses:          %d\n",
 417                             dimmInfo->numOfColAddresses);
 418                        break;
 419/*------------------------------------------------------------------------------------------------------------------------------*/
 420
 421                case 5: /* Number Of Module Banks */
 422                        dimmInfo->numOfModuleBanks = data[i];
 423                        debug("Number of Banks on Mod. :                                %d\n",
 424                             dimmInfo->numOfModuleBanks);
 425                        break;
 426/*------------------------------------------------------------------------------------------------------------------------------*/
 427
 428                case 6: /* Data Width */
 429                        dimmInfo->dataWidth = data[i];
 430                        debug("Module Data Width:                               %d\n",
 431                             dimmInfo->dataWidth);
 432                        break;
 433/*------------------------------------------------------------------------------------------------------------------------------*/
 434
 435                case 8: /* Voltage Interface */
 436                        switch (data[i]) {
 437                        case 0x0:
 438                                dimmInfo->voltageInterface = TTL_5V_TOLERANT;
 439                                debug("Module is                                        TTL_5V_TOLERANT\n");
 440                                break;
 441                        case 0x1:
 442                                dimmInfo->voltageInterface = LVTTL;
 443                                debug("Module is                                        LVTTL\n");
 444                                break;
 445                        case 0x2:
 446                                dimmInfo->voltageInterface = HSTL_1_5V;
 447                                debug("Module is                                        TTL_5V_TOLERANT\n");
 448                                break;
 449                        case 0x3:
 450                                dimmInfo->voltageInterface = SSTL_3_3V;
 451                                debug("Module is                                        HSTL_1_5V\n");
 452                                break;
 453                        case 0x4:
 454                                dimmInfo->voltageInterface = SSTL_2_5V;
 455                                debug("Module is                                        SSTL_2_5V\n");
 456                                break;
 457                        default:
 458                                dimmInfo->voltageInterface = VOLTAGE_UNKNOWN;
 459                                debug("Module is                                        VOLTAGE_UNKNOWN\n");
 460                                break;
 461                        }
 462                        break;
 463/*------------------------------------------------------------------------------------------------------------------------------*/
 464
 465                case 9: /* Minimum Cycle Time At Max CasLatancy */
 466                        shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
 467                        mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
 468                        maskLeftOfPoint =
 469                                (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
 470                        maskRightOfPoint =
 471                                (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
 472                        leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
 473                        rightOfPoint = (data[i] & maskRightOfPoint) * mult;
 474                        dimmInfo->minimumCycleTimeAtMaxCasLatancy_LoP =
 475                                leftOfPoint;
 476                        dimmInfo->minimumCycleTimeAtMaxCasLatancy_RoP =
 477                                rightOfPoint;
 478                        debug("Minimum Cycle Time At Max CasLatancy:            %d.%d [ns]\n",
 479                             leftOfPoint, rightOfPoint);
 480                        break;
 481/*------------------------------------------------------------------------------------------------------------------------------*/
 482
 483                case 10:        /* Clock To Data Out */
 484                        div = (dimmInfo->memoryType == DDR) ? 100 : 10;
 485                        time_tmp =
 486                                (((data[i] & 0xf0) >> 4) * 10) +
 487                                ((data[i] & 0x0f));
 488                        leftOfPoint = time_tmp / div;
 489                        rightOfPoint = time_tmp % div;
 490                        dimmInfo->clockToDataOut_LoP = leftOfPoint;
 491                        dimmInfo->clockToDataOut_RoP = rightOfPoint;
 492                        debug("Clock To Data Out:                               %d.%2d [ns]\n",
 493                             leftOfPoint, rightOfPoint);
 494                        /*dimmInfo->clockToDataOut */
 495                        break;
 496/*------------------------------------------------------------------------------------------------------------------------------*/
 497
 498#ifdef CONFIG_MV64360_ECC
 499                case 11:        /* Error Check Type */
 500                        dimmInfo->errorCheckType = data[i];
 501                        debug("Error Check Type (0=NONE):                       %d\n",
 502                             dimmInfo->errorCheckType);
 503                        break;
 504#endif /* of ifdef CONFIG_MV64360_ECC */
 505/*------------------------------------------------------------------------------------------------------------------------------*/
 506
 507                case 12:        /* Refresh Interval */
 508                        dimmInfo->RefreshInterval = data[i];
 509                        debug("RefreshInterval (80= Self refresh Normal, 15.625us) : %x\n",
 510                             dimmInfo->RefreshInterval);
 511                        break;
 512/*------------------------------------------------------------------------------------------------------------------------------*/
 513
 514                case 13:        /* Sdram Width */
 515                        dimmInfo->sdramWidth = data[i];
 516                        debug("Sdram Width:                                     %d\n",
 517                             dimmInfo->sdramWidth);
 518                        break;
 519/*------------------------------------------------------------------------------------------------------------------------------*/
 520
 521                case 14:        /* Error Check Data Width */
 522                        dimmInfo->errorCheckDataWidth = data[i];
 523                        debug("Error Check Data Width:                  %d\n",
 524                             dimmInfo->errorCheckDataWidth);
 525                        break;
 526/*------------------------------------------------------------------------------------------------------------------------------*/
 527
 528                case 15:        /* Minimum Clock Delay */
 529                        dimmInfo->minClkDelay = data[i];
 530                        debug("Minimum Clock Delay:                             %d\n",
 531                             dimmInfo->minClkDelay);
 532                        break;
 533/*------------------------------------------------------------------------------------------------------------------------------*/
 534
 535                case 16:        /* Burst Length Supported */
 536                           /******-******-******-*******
 537                           * bit3 | bit2 | bit1 | bit0 *
 538                           *******-******-******-*******
 539            burst length = *  8   |  4   |   2  |   1  *
 540                           *****************************
 541
 542            If for example bit0 and bit2 are set, the burst
 543            length supported are 1 and 4. */
 544
 545                        dimmInfo->burstLengthSupported = data[i];
 546#ifdef DEBUG
 547                        debug("Burst Length Supported:                  ");
 548                        if (dimmInfo->burstLengthSupported & 0x01)
 549                                debug("1, ");
 550                        if (dimmInfo->burstLengthSupported & 0x02)
 551                                debug("2, ");
 552                        if (dimmInfo->burstLengthSupported & 0x04)
 553                                debug("4, ");
 554                        if (dimmInfo->burstLengthSupported & 0x08)
 555                                debug("8, ");
 556                        debug(" Bit \n");
 557#endif
 558                        break;
 559/*------------------------------------------------------------------------------------------------------------------------------*/
 560
 561                case 17:        /* Number Of Banks On Each Device */
 562                        dimmInfo->numOfBanksOnEachDevice = data[i];
 563                        debug("Number Of Banks On Each Chip:                    %d\n",
 564                             dimmInfo->numOfBanksOnEachDevice);
 565                        break;
 566/*------------------------------------------------------------------------------------------------------------------------------*/
 567
 568                case 18:        /* Suported Cas Latencies */
 569
 570                        /*     DDR:
 571                         *******-******-******-******-******-******-******-*******
 572                         * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
 573                         *******-******-******-******-******-******-******-*******
 574                         CAS =   * TBD  | TBD  | 3.5  |   3  | 2.5  |  2   | 1.5  |   1  *
 575                         *********************************************************
 576                         SDRAM:
 577                         *******-******-******-******-******-******-******-*******
 578                         * bit7 | bit6 | bit5 | bit4 | bit3 | bit2 | bit1 | bit0 *
 579                         *******-******-******-******-******-******-******-*******
 580                         CAS =   * TBD  |  7   |  6   |  5   |  4   |  3   |   2  |   1  *
 581                         ********************************************************/
 582                        dimmInfo->suportedCasLatencies = data[i];
 583#ifdef DEBUG
 584                        debug("Suported Cas Latencies: (CL)                     ");
 585                        if (dimmInfo->memoryType == 0) {        /* SDRAM */
 586                                for (k = 0; k <= 7; k++) {
 587                                        if (dimmInfo->
 588                                            suportedCasLatencies & (1 << k))
 589                                                debug("%d,                      ",
 590                                                     k + 1);
 591                                }
 592
 593                        } else {        /* DDR-RAM */
 594
 595                                if (dimmInfo->suportedCasLatencies & 1)
 596                                        debug("1, ");
 597                                if (dimmInfo->suportedCasLatencies & 2)
 598                                        debug("1.5, ");
 599                                if (dimmInfo->suportedCasLatencies & 4)
 600                                        debug("2, ");
 601                                if (dimmInfo->suportedCasLatencies & 8)
 602                                        debug("2.5, ");
 603                                if (dimmInfo->suportedCasLatencies & 16)
 604                                        debug("3, ");
 605                                if (dimmInfo->suportedCasLatencies & 32)
 606                                        debug("3.5, ");
 607
 608                        }
 609                        debug("\n");
 610#endif
 611                        /* Calculating MAX CAS latency */
 612                        for (j = 7; j > 0; j--) {
 613                                if (((dimmInfo->
 614                                      suportedCasLatencies >> j) & 0x1) ==
 615                                    1) {
 616                                        switch (dimmInfo->memoryType) {
 617                                        case DDR:
 618                                                /* CAS latency 1, 1.5, 2, 2.5, 3, 3.5 */
 619                                                switch (j) {
 620                                                case 7:
 621                                                        debug("Max. Cas Latencies (DDR):                        ERROR !!!\n");
 622                                                        dimmInfo->
 623                                                                maxClSupported_DDR
 624                                                                =
 625                                                                DDR_CL_FAULT;
 626                                                        hang ();
 627                                                        break;
 628                                                case 6:
 629                                                        debug("Max. Cas Latencies (DDR):                        ERROR !!!\n");
 630                                                        dimmInfo->
 631                                                                maxClSupported_DDR
 632                                                                =
 633                                                                DDR_CL_FAULT;
 634                                                        hang ();
 635                                                        break;
 636                                                case 5:
 637                                                        debug("Max. Cas Latencies (DDR):                        3.5 clk's\n");
 638                                                        dimmInfo->
 639                                                                maxClSupported_DDR
 640                                                                = DDR_CL_3_5;
 641                                                        break;
 642                                                case 4:
 643                                                        debug("Max. Cas Latencies (DDR):                        3 clk's \n");
 644                                                        dimmInfo->
 645                                                                maxClSupported_DDR
 646                                                                = DDR_CL_3;
 647                                                        break;
 648                                                case 3:
 649                                                        debug("Max. Cas Latencies (DDR):                        2.5 clk's \n");
 650                                                        dimmInfo->
 651                                                                maxClSupported_DDR
 652                                                                = DDR_CL_2_5;
 653                                                        break;
 654                                                case 2:
 655                                                        debug("Max. Cas Latencies (DDR):                        2 clk's \n");
 656                                                        dimmInfo->
 657                                                                maxClSupported_DDR
 658                                                                = DDR_CL_2;
 659                                                        break;
 660                                                case 1:
 661                                                        debug("Max. Cas Latencies (DDR):                        1.5 clk's \n");
 662                                                        dimmInfo->
 663                                                                maxClSupported_DDR
 664                                                                = DDR_CL_1_5;
 665                                                        break;
 666                                                }
 667                                                dimmInfo->
 668                                                        maxCASlatencySupported_LoP
 669                                                        =
 670                                                        1 +
 671                                                        (int) (5 * j / 10);
 672                                                if (((5 * j) % 10) != 0)
 673                                                        dimmInfo->
 674                                                                maxCASlatencySupported_RoP
 675                                                                = 5;
 676                                                else
 677                                                        dimmInfo->
 678                                                                maxCASlatencySupported_RoP
 679                                                                = 0;
 680                                                debug("Max. Cas Latencies (DDR LoP.RoP Notation):       %d.%d \n",
 681                                                     dimmInfo->
 682                                                     maxCASlatencySupported_LoP,
 683                                                     dimmInfo->
 684                                                     maxCASlatencySupported_RoP);
 685                                                break;
 686                                        case SDRAM:
 687                                                /* CAS latency 1, 2, 3, 4, 5, 6, 7 */
 688                                                dimmInfo->maxClSupported_SD = j;        /*  Cas Latency DDR-RAM Coded                   */
 689                                                debug("Max. Cas Latencies (SD): %d\n",
 690                                                     dimmInfo->
 691                                                     maxClSupported_SD);
 692                                                dimmInfo->
 693                                                        maxCASlatencySupported_LoP
 694                                                        = j;
 695                                                dimmInfo->
 696                                                        maxCASlatencySupported_RoP
 697                                                        = 0;
 698                                                debug("Max. Cas Latencies (DDR LoP.RoP Notation): %d.%d \n",
 699                                                     dimmInfo->
 700                                                     maxCASlatencySupported_LoP,
 701                                                     dimmInfo->
 702                                                     maxCASlatencySupported_RoP);
 703                                                break;
 704                                        }
 705                                        break;
 706                                }
 707                        }
 708                        break;
 709/*------------------------------------------------------------------------------------------------------------------------------*/
 710
 711                case 21:        /* Buffered Address And Control Inputs */
 712                        debug("\nModul Attributes (SPD Byte 21): \n");
 713                        dimmInfo->bufferedAddrAndControlInputs =
 714                                data[i] & BIT0;
 715                        dimmInfo->registeredAddrAndControlInputs =
 716                                (data[i] & BIT1) >> 1;
 717                        dimmInfo->onCardPLL = (data[i] & BIT2) >> 2;
 718                        dimmInfo->bufferedDQMBinputs = (data[i] & BIT3) >> 3;
 719                        dimmInfo->registeredDQMBinputs =
 720                                (data[i] & BIT4) >> 4;
 721                        dimmInfo->differentialClockInput =
 722                                (data[i] & BIT5) >> 5;
 723                        dimmInfo->redundantRowAddressing =
 724                                (data[i] & BIT6) >> 6;
 725
 726                        if (dimmInfo->bufferedAddrAndControlInputs == 1)
 727                                debug(" - Buffered Address/Control Input:               Yes \n");
 728                        else
 729                                debug(" - Buffered Address/Control Input:               No \n");
 730
 731                        if (dimmInfo->registeredAddrAndControlInputs == 1)
 732                                debug(" - Registered Address/Control Input:             Yes \n");
 733                        else
 734                                debug(" - Registered Address/Control Input:             No \n");
 735
 736                        if (dimmInfo->onCardPLL == 1)
 737                                debug(" - On-Card PLL (clock):                          Yes \n");
 738                        else
 739                                debug(" - On-Card PLL (clock):                          No \n");
 740
 741                        if (dimmInfo->bufferedDQMBinputs == 1)
 742                                debug(" - Bufferd DQMB Inputs:                          Yes \n");
 743                        else
 744                                debug(" - Bufferd DQMB Inputs:                          No \n");
 745
 746                        if (dimmInfo->registeredDQMBinputs == 1)
 747                                debug(" - Registered DQMB Inputs:                       Yes \n");
 748                        else
 749                                debug(" - Registered DQMB Inputs:                       No \n");
 750
 751                        if (dimmInfo->differentialClockInput == 1)
 752                                debug(" - Differential Clock Input:                     Yes \n");
 753                        else
 754                                debug(" - Differential Clock Input:                     No \n");
 755
 756                        if (dimmInfo->redundantRowAddressing == 1)
 757                                debug(" - redundant Row Addressing:                     Yes \n");
 758                        else
 759                                debug(" - redundant Row Addressing:                     No \n");
 760
 761                        break;
 762/*------------------------------------------------------------------------------------------------------------------------------*/
 763
 764                case 22:        /* Suported AutoPreCharge */
 765                        debug("\nModul Attributes (SPD Byte 22): \n");
 766                        dimmInfo->suportedEarlyRasPreCharge = data[i] & BIT0;
 767                        dimmInfo->suportedAutoPreCharge =
 768                                (data[i] & BIT1) >> 1;
 769                        dimmInfo->suportedPreChargeAll =
 770                                (data[i] & BIT2) >> 2;
 771                        dimmInfo->suportedWrite1ReadBurst =
 772                                (data[i] & BIT3) >> 3;
 773                        dimmInfo->suported5PercentLowVCC =
 774                                (data[i] & BIT4) >> 4;
 775                        dimmInfo->suported5PercentUpperVCC =
 776                                (data[i] & BIT5) >> 5;
 777
 778                        if (dimmInfo->suportedEarlyRasPreCharge == 1)
 779                                debug(" - Early Ras Precharge:                  Yes \n");
 780                        else
 781                                debug(" -  Early Ras Precharge:                 No \n");
 782
 783                        if (dimmInfo->suportedAutoPreCharge == 1)
 784                                debug(" - AutoPreCharge:                                Yes \n");
 785                        else
 786                                debug(" -  AutoPreCharge:                               No \n");
 787
 788                        if (dimmInfo->suportedPreChargeAll == 1)
 789                                debug(" - Precharge All:                                Yes \n");
 790                        else
 791                                debug(" -  Precharge All:                               No \n");
 792
 793                        if (dimmInfo->suportedWrite1ReadBurst == 1)
 794                                debug(" - Write 1/ReadBurst:                            Yes \n");
 795                        else
 796                                debug(" -  Write 1/ReadBurst:                           No \n");
 797
 798                        if (dimmInfo->suported5PercentLowVCC == 1)
 799                                debug(" - lower VCC tolerance:                  5 Percent \n");
 800                        else
 801                                debug(" - lower VCC tolerance:                  10 Percent \n");
 802
 803                        if (dimmInfo->suported5PercentUpperVCC == 1)
 804                                debug(" - upper VCC tolerance:                  5 Percent \n");
 805                        else
 806                                debug(" -  upper VCC tolerance:                 10 Percent \n");
 807
 808                        break;
 809/*------------------------------------------------------------------------------------------------------------------------------*/
 810
 811                case 23:        /* Minimum Cycle Time At Maximum Cas Latancy Minus 1 (2nd highest CL) */
 812                        shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
 813                        mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
 814                        maskLeftOfPoint =
 815                                (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
 816                        maskRightOfPoint =
 817                                (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
 818                        leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
 819                        rightOfPoint = (data[i] & maskRightOfPoint) * mult;
 820                        dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_LoP =
 821                                leftOfPoint;
 822                        dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus1_RoP =
 823                                rightOfPoint;
 824                        debug("Minimum Cycle Time At 2nd highest CasLatancy (0 = Not supported): %d.%d [ns]\n",
 825                             leftOfPoint, rightOfPoint);
 826                        /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
 827                        break;
 828/*------------------------------------------------------------------------------------------------------------------------------*/
 829
 830                case 24:        /* Clock To Data Out 2nd highest Cas Latency Value */
 831                        div = (dimmInfo->memoryType == DDR) ? 100 : 10;
 832                        time_tmp =
 833                                (((data[i] & 0xf0) >> 4) * 10) +
 834                                ((data[i] & 0x0f));
 835                        leftOfPoint = time_tmp / div;
 836                        rightOfPoint = time_tmp % div;
 837                        dimmInfo->clockToDataOutMinus1_LoP = leftOfPoint;
 838                        dimmInfo->clockToDataOutMinus1_RoP = rightOfPoint;
 839                        debug("Clock To Data Out (2nd CL value):                %d.%2d [ns]\n",
 840                             leftOfPoint, rightOfPoint);
 841                        break;
 842/*------------------------------------------------------------------------------------------------------------------------------*/
 843
 844                case 25:        /* Minimum Cycle Time At Maximum Cas Latancy Minus 2 (3rd highest CL) */
 845                        shift = (dimmInfo->memoryType == DDR) ? 4 : 2;
 846                        mult = (dimmInfo->memoryType == DDR) ? 10 : 25;
 847                        maskLeftOfPoint =
 848                                (dimmInfo->memoryType == DDR) ? 0xf0 : 0xfc;
 849                        maskRightOfPoint =
 850                                (dimmInfo->memoryType == DDR) ? 0xf : 0x03;
 851                        leftOfPoint = (data[i] & maskLeftOfPoint) >> shift;
 852                        rightOfPoint = (data[i] & maskRightOfPoint) * mult;
 853                        dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_LoP =
 854                                leftOfPoint;
 855                        dimmInfo->minimumCycleTimeAtMaxCasLatancyMinus2_RoP =
 856                                rightOfPoint;
 857                        debug("Minimum Cycle Time At 3rd highest CasLatancy (0 = Not supported): %d.%d [ns]\n",
 858                             leftOfPoint, rightOfPoint);
 859                        /*dimmInfo->minimumCycleTimeAtMaxCasLatancy */
 860                        break;
 861/*------------------------------------------------------------------------------------------------------------------------------*/
 862
 863                case 26:        /* Clock To Data Out 3rd highest Cas Latency Value */
 864                        div = (dimmInfo->memoryType == DDR) ? 100 : 10;
 865                        time_tmp =
 866                                (((data[i] & 0xf0) >> 4) * 10) +
 867                                ((data[i] & 0x0f));
 868                        leftOfPoint = time_tmp / div;
 869                        rightOfPoint = time_tmp % div;
 870                        dimmInfo->clockToDataOutMinus2_LoP = leftOfPoint;
 871                        dimmInfo->clockToDataOutMinus2_RoP = rightOfPoint;
 872                        debug("Clock To Data Out (3rd CL value):                %d.%2d [ns]\n",
 873                             leftOfPoint, rightOfPoint);
 874                        break;
 875/*------------------------------------------------------------------------------------------------------------------------------*/
 876
 877                case 27:        /* Minimum Row Precharge Time */
 878                        shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
 879                        maskLeftOfPoint =
 880                                (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
 881                        maskRightOfPoint =
 882                                (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
 883                        leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
 884                        rightOfPoint = (data[i] & maskRightOfPoint) * 25;
 885
 886                        dimmInfo->minRowPrechargeTime = ((leftOfPoint * 100) + rightOfPoint);   /* measured in n times 10ps Intervals */
 887                        trp_clocks =
 888                                (dimmInfo->minRowPrechargeTime +
 889                                 (tmemclk - 1)) / tmemclk;
 890                        debug("*** 1 clock cycle = %ld  10ps intervalls = %ld.%ld ns****\n",
 891                             tmemclk, tmemclk / 100, tmemclk % 100);
 892                        debug("Minimum Row Precharge Time [ns]:         %d.%2d = in Clk cycles %d\n",
 893                             leftOfPoint, rightOfPoint, trp_clocks);
 894                        break;
 895/*------------------------------------------------------------------------------------------------------------------------------*/
 896
 897                case 28:        /* Minimum Row Active to Row Active Time */
 898                        shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
 899                        maskLeftOfPoint =
 900                                (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
 901                        maskRightOfPoint =
 902                                (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
 903                        leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
 904                        rightOfPoint = (data[i] & maskRightOfPoint) * 25;
 905
 906                        dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint);    /* measured in 100ns Intervals */
 907                        debug("Minimum Row Active -To- Row Active Delay [ns]:   %d.%2d = in Clk cycles %d\n",
 908                             leftOfPoint, rightOfPoint, trp_clocks);
 909                        break;
 910/*------------------------------------------------------------------------------------------------------------------------------*/
 911
 912                case 29:        /* Minimum Ras-To-Cas Delay */
 913                        shift = (dimmInfo->memoryType == DDR) ? 2 : 0;
 914                        maskLeftOfPoint =
 915                                (dimmInfo->memoryType == DDR) ? 0xfc : 0xff;
 916                        maskRightOfPoint =
 917                                (dimmInfo->memoryType == DDR) ? 0x03 : 0x00;
 918                        leftOfPoint = ((data[i] & maskLeftOfPoint) >> shift);
 919                        rightOfPoint = (data[i] & maskRightOfPoint) * 25;
 920
 921                        dimmInfo->minRowActiveRowActiveDelay = ((leftOfPoint * 100) + rightOfPoint);    /* measured in 100ns Intervals */
 922                        debug("Minimum Ras-To-Cas Delay [ns]:                   %d.%2d = in Clk cycles %d\n",
 923                             leftOfPoint, rightOfPoint, trp_clocks);
 924                        break;
 925/*------------------------------------------------------------------------------------------------------------------------------*/
 926
 927                case 30:        /* Minimum Ras Pulse Width */
 928                        dimmInfo->minRasPulseWidth = data[i];
 929                        tras_clocks =
 930                                (NSto10PS (data[i]) +
 931                                 (tmemclk - 1)) / tmemclk;
 932                        debug("Minimum Ras Pulse Width [ns]:                    %d = in Clk cycles %d\n",
 933                             dimmInfo->minRasPulseWidth, tras_clocks);
 934
 935                        break;
 936/*------------------------------------------------------------------------------------------------------------------------------*/
 937
 938                case 31:        /* Module Bank Density */
 939                        dimmInfo->moduleBankDensity = data[i];
 940                        debug("Module Bank Density:                             %d\n",
 941                             dimmInfo->moduleBankDensity);
 942#ifdef DEBUG
 943                        debug("*** Offered Densities (more than 1 = Multisize-Module): ");
 944                        {
 945                                if (dimmInfo->moduleBankDensity & 1)
 946                                        debug("4MB, ");
 947                                if (dimmInfo->moduleBankDensity & 2)
 948                                        debug("8MB, ");
 949                                if (dimmInfo->moduleBankDensity & 4)
 950                                        debug("16MB, ");
 951                                if (dimmInfo->moduleBankDensity & 8)
 952                                        debug("32MB, ");
 953                                if (dimmInfo->moduleBankDensity & 16)
 954                                        debug("64MB, ");
 955                                if (dimmInfo->moduleBankDensity & 32)
 956                                        debug("128MB, ");
 957                                if ((dimmInfo->moduleBankDensity & 64)
 958                                    || (dimmInfo->moduleBankDensity & 128)) {
 959                                        debug("ERROR, ");
 960                                        hang ();
 961                                }
 962                        }
 963                        debug("\n");
 964#endif
 965                        break;
 966/*------------------------------------------------------------------------------------------------------------------------------*/
 967
 968                case 32:        /* Address And Command Setup Time (measured in ns/1000) */
 969                        sign = 1;
 970                        switch (dimmInfo->memoryType) {
 971                        case DDR:
 972                                time_tmp =
 973                                        (((data[i] & 0xf0) >> 4) * 10) +
 974                                        ((data[i] & 0x0f));
 975                                leftOfPoint = time_tmp / 100;
 976                                rightOfPoint = time_tmp % 100;
 977                                break;
 978                        case SDRAM:
 979                                leftOfPoint = (data[i] & 0xf0) >> 4;
 980                                if (leftOfPoint > 7) {
 981                                        leftOfPoint = data[i] & 0x70 >> 4;
 982                                        sign = -1;
 983                                }
 984                                rightOfPoint = (data[i] & 0x0f);
 985                                break;
 986                        }
 987                        dimmInfo->addrAndCommandSetupTime =
 988                                (leftOfPoint * 100 + rightOfPoint) * sign;
 989                        debug("Address And Command Setup Time [ns]:             %d.%d\n",
 990                             sign * leftOfPoint, rightOfPoint);
 991                        break;
 992/*------------------------------------------------------------------------------------------------------------------------------*/
 993
 994                case 33:        /* Address And Command Hold Time */
 995                        sign = 1;
 996                        switch (dimmInfo->memoryType) {
 997                        case DDR:
 998                                time_tmp =
 999                                        (((data[i] & 0xf0) >> 4) * 10) +
1000                                        ((data[i] & 0x0f));

1001                                leftOfPoint = time_tmp / 100;
1002                                rightOfPoint = time_tmp % 100;
1003                                break;
1004                        case SDRAM:
1005                                leftOfPoint = (data[i] & 0xf0) >> 4;
1006                                if (leftOfPoint > 7) {
1007                                        leftOfPoint = data[i] & 0x70 >> 4;
1008                                        sign = -1;
1009                                }
1010                                rightOfPoint = (data[i] & 0x0f);
1011                                break;
1012                        }
1013                        dimmInfo->addrAndCommandHoldTime =
1014                                (leftOfPoint * 100 + rightOfPoint) * sign;
1015                        debug("Address And Command Hold Time [ns]:              %d.%d\n",
1016                             sign * leftOfPoint, rightOfPoint);
1017                        break;
1018/*------------------------------------------------------------------------------------------------------------------------------*/
1019
1020                case 34:        /* Data Input Setup Time */
1021                        sign = 1;
1022                        switch (dimmInfo->memoryType) {
1023                        case DDR:
1024                                time_tmp =
1025                                        (((data[i] & 0xf0) >> 4) * 10) +
1026                                        ((data[i] & 0x0f));
1027                                leftOfPoint = time_tmp / 100;
1028                                rightOfPoint = time_tmp % 100;
1029                                break;
1030                        case SDRAM:
1031                                leftOfPoint = (data[i] & 0xf0) >> 4;
1032                                if (leftOfPoint > 7) {
1033                                        leftOfPoint = data[i] & 0x70 >> 4;
1034                                        sign = -1;
1035                                }
1036                                rightOfPoint = (data[i] & 0x0f);
1037                                break;
1038                        }
1039                        dimmInfo->dataInputSetupTime =
1040                                (leftOfPoint * 100 + rightOfPoint) * sign;
1041                        debug("Data Input Setup Time [ns]:                      %d.%d\n",
1042                             sign * leftOfPoint, rightOfPoint);
1043                        break;
1044/*------------------------------------------------------------------------------------------------------------------------------*/
1045
1046                case 35:        /* Data Input Hold Time */
1047                        sign = 1;
1048                        switch (dimmInfo->memoryType) {
1049                        case DDR:
1050                                time_tmp =
1051                                        (((data[i] & 0xf0) >> 4) * 10) +
1052                                        ((data[i] & 0x0f));
1053                                leftOfPoint = time_tmp / 100;
1054                                rightOfPoint = time_tmp % 100;
1055                                break;
1056                        case SDRAM:
1057                                leftOfPoint = (data[i] & 0xf0) >> 4;
1058                                if (leftOfPoint > 7) {
1059                                        leftOfPoint = data[i] & 0x70 >> 4;
1060                                        sign = -1;
1061                                }
1062                                rightOfPoint = (data[i] & 0x0f);
1063                                break;
1064                        }
1065                        dimmInfo->dataInputHoldTime =
1066                                (leftOfPoint * 100 + rightOfPoint) * sign;
1067                        debug("Data Input Hold Time [ns]:                       %d.%d\n\n",
1068                             sign * leftOfPoint, rightOfPoint);
1069                        break;
1070/*------------------------------------------------------------------------------------------------------------------------------*/
1071                }
1072        }
1073        /* calculating the sdram density */
1074        for (i = 0;
1075             i < dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses;
1076             i++) {
1077                density = density * 2;
1078        }
1079        dimmInfo->deviceDensity = density * dimmInfo->numOfBanksOnEachDevice *
1080                dimmInfo->sdramWidth;
1081        dimmInfo->numberOfDevices =
1082                (dimmInfo->dataWidth / dimmInfo->sdramWidth) *
1083                dimmInfo->numOfModuleBanks;
1084        devicesForErrCheck =
1085                (dimmInfo->dataWidth - 64) / dimmInfo->sdramWidth;
1086        if ((dimmInfo->errorCheckType == 0x1)
1087            || (dimmInfo->errorCheckType == 0x2)
1088            || (dimmInfo->errorCheckType == 0x3)) {
1089                dimmInfo->size =
1090                        (dimmInfo->deviceDensity / 8) *
1091                        (dimmInfo->numberOfDevices - devicesForErrCheck);
1092        } else {
1093                dimmInfo->size =
1094                        (dimmInfo->deviceDensity / 8) *
1095                        dimmInfo->numberOfDevices;
1096        }
1097
1098        /* compute the module DRB size */
1099        tmp = (1 <<
1100               (dimmInfo->numOfRowAddresses + dimmInfo->numOfColAddresses));
1101        tmp *= dimmInfo->numOfModuleBanks;
1102        tmp *= dimmInfo->sdramWidth;
1103        tmp = tmp >> 24;        /* div by 0x4000000 (64M)       */
1104        dimmInfo->drb_size = (uchar) tmp;
1105        debug("Module DRB size (n*64Mbit): %d\n", dimmInfo->drb_size);
1106
1107        /* try a CAS latency of 3 first... */
1108
1109        /* bit 1 is CL2, bit 2 is CL3 */
1110        supp_cal = (dimmInfo->suportedCasLatencies & 0x1c) >> 1;
1111
1112        cal_val = 0;
1113        if (supp_cal & 8) {
1114                if (NS10to10PS (data[9]) <= tmemclk)
1115                        cal_val = 6;
1116        }
1117        if (supp_cal & 4) {
1118                if (NS10to10PS (data[9]) <= tmemclk)
1119                        cal_val = 5;
1120        }
1121
1122        /* then 2... */
1123        if (supp_cal & 2) {
1124                if (NS10to10PS (data[23]) <= tmemclk)
1125                        cal_val = 4;
1126        }
1127
1128        debug("cal_val = %d\n", cal_val * 5);
1129
1130        /* bummer, did't work... */
1131        if (cal_val == 0) {
1132                debug("Couldn't find a good CAS latency\n");
1133                hang ();
1134                return 0;
1135        }
1136
1137        return true;
1138}
1139
1140/* sets up the GT properly with information passed in */
1141int setup_sdram (AUX_MEM_DIMM_INFO * info)
1142{
1143        ulong tmp;
1144        ulong tmp_sdram_mode = 0;       /* 0x141c */
1145        ulong tmp_dunit_control_low = 0;        /* 0x1404 */
1146        uint sdram_config_reg = CONFIG_SYS_SDRAM_CONFIG;
1147        int i;
1148
1149        /* sanity checking */
1150        if (!info->numOfModuleBanks) {
1151                printf ("setup_sdram called with 0 banks\n");
1152                return 1;
1153        }
1154
1155        /* delay line */
1156
1157        /* Program the GT with the discovered data */
1158        if (info->registeredAddrAndControlInputs == true)
1159                debug("Module is registered, but we do not support registered Modules !!!\n");
1160
1161        /* delay line */
1162        set_dfcdlInit ();       /* may be its not needed */
1163        debug("Delay line set done\n");
1164
1165        /* set SDRAM mode NOP */ /* To_do check it */
1166        GT_REG_WRITE (SDRAM_OPERATION, 0x5);
1167        while (GTREGREAD (SDRAM_OPERATION) != 0) {
1168                debug("\n*** SDRAM_OPERATION 1418: Module still busy ... please wait... ***\n");
1169        }
1170
1171#ifdef CONFIG_MV64360_ECC
1172        if ((info->errorCheckType == 0x2) && (CPCI750_ECC_TEST)) {
1173                /* DRAM has ECC, so turn it on */
1174                sdram_config_reg |= BIT18;
1175                debug("Enabling ECC\n");
1176        }
1177#endif /* of ifdef CONFIG_MV64360_ECC */
1178
1179        /* SDRAM configuration */
1180        GT_REG_WRITE(SDRAM_CONFIG, sdram_config_reg);
1181        debug("sdram_conf 0x1400: %08x\n", GTREGREAD (SDRAM_CONFIG));
1182
1183        /* SDRAM open pages controll keep open as much as I can */
1184        GT_REG_WRITE (SDRAM_OPEN_PAGES_CONTROL, 0x0);
1185        debug("sdram_open_pages_controll 0x1414: %08x\n",
1186             GTREGREAD (SDRAM_OPEN_PAGES_CONTROL));
1187
1188
1189        /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
1190        tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01);  /* Clock Domain Sync from power on reset */
1191        if (tmp == 0)
1192                debug("Core Signals are sync (by HW-Setting)!!!\n");
1193        else
1194                debug("Core Signals syncs. are bypassed (by HW-Setting)!!!\n");
1195
1196        /* SDRAM set CAS Lentency according to SPD information */
1197        switch (info->memoryType) {
1198        case SDRAM:
1199                debug("### SD-RAM not supported yet !!!\n");
1200                hang ();
1201                /* ToDo fill SD-RAM if needed !!!!! */
1202                break;
1203
1204        case DDR:
1205                debug("### SET-CL for DDR-RAM\n");
1206
1207                switch (info->maxClSupported_DDR) {
1208                case DDR_CL_3:
1209                        tmp_dunit_control_low = 0x3c000000;     /* Read-Data sampled on falling edge of Clk */
1210                        tmp_sdram_mode = 0x32;  /* CL=3 Burstlength = 4 */
1211                        debug("Max. CL is 3 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1212                             tmp_sdram_mode, tmp_dunit_control_low);
1213                        break;
1214
1215                case DDR_CL_2_5:
1216                        if (tmp == 1) { /* clocks sync */
1217                                tmp_dunit_control_low = 0x24000000;     /* Read-Data sampled on falling edge of Clk */
1218                                tmp_sdram_mode = 0x62;  /* CL=2,5 Burstlength = 4 */
1219                                debug("Max. CL is 2,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1220                                     tmp_sdram_mode, tmp_dunit_control_low);
1221                        } else {        /* clk sync. bypassed     */
1222
1223                                tmp_dunit_control_low = 0x03000000;     /* Read-Data sampled on rising edge of Clk */
1224                                tmp_sdram_mode = 0x62;  /* CL=2,5 Burstlength = 4 */
1225                                debug("Max. CL is 2,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1226                                     tmp_sdram_mode, tmp_dunit_control_low);
1227                        }
1228                        break;
1229
1230                case DDR_CL_2:
1231                        if (tmp == 1) { /* Sync */
1232                                tmp_dunit_control_low = 0x03000000;     /* Read-Data sampled on rising edge of Clk */
1233                                tmp_sdram_mode = 0x22;  /* CL=2 Burstlength = 4 */
1234                                debug("Max. CL is 2s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1235                                     tmp_sdram_mode, tmp_dunit_control_low);
1236                        } else {        /* Not sync.      */
1237
1238                                tmp_dunit_control_low = 0x3b000000;     /* Read-Data sampled on rising edge of Clk */
1239                                tmp_sdram_mode = 0x22;  /* CL=2 Burstlength = 4 */
1240                                debug("Max. CL is 2 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1241                                     tmp_sdram_mode, tmp_dunit_control_low);
1242                        }
1243                        break;
1244
1245                case DDR_CL_1_5:
1246                        if (tmp == 1) { /* Sync */
1247                                tmp_dunit_control_low = 0x23000000;     /* Read-Data sampled on falling edge of Clk */
1248                                tmp_sdram_mode = 0x52;  /* CL=1,5 Burstlength = 4 */
1249                                debug("Max. CL is 1,5s CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1250                                     tmp_sdram_mode, tmp_dunit_control_low);
1251                        } else {        /* not sync */
1252
1253                                tmp_dunit_control_low = 0x1a000000;     /* Read-Data sampled on rising edge of Clk */
1254                                tmp_sdram_mode = 0x52;  /* CL=1,5 Burstlength = 4 */
1255                                debug("Max. CL is 1,5 CLKs 0x141c= %08lx, 0x1404 = %08lx\n",
1256                                     tmp_sdram_mode, tmp_dunit_control_low);
1257                        }
1258                        break;
1259
1260                default:
1261                        printf ("Max. CL is out of range %d\n",
1262                                info->maxClSupported_DDR);
1263                        hang ();
1264                        break;
1265                }
1266                break;
1267        }
1268
1269        /* Write results of CL detection procedure */
1270        GT_REG_WRITE (SDRAM_MODE, tmp_sdram_mode);
1271        /* set SDRAM mode SetCommand 0x1418 */
1272        GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1273        while (GTREGREAD (SDRAM_OPERATION) != 0) {
1274                debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
1275        }
1276
1277
1278        /* SDRAM D_UNIT_CONTROL_LOW 0x1404 */
1279        tmp = (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x01);  /* Clock Domain Sync from power on reset */
1280        if (tmp != 1) {         /*clocks are not sync */
1281                /* asyncmode */
1282                GT_REG_WRITE (D_UNIT_CONTROL_LOW,
1283                              (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x7F) |
1284                              0x18110780 | tmp_dunit_control_low);
1285        } else {
1286                /* syncmode */
1287                GT_REG_WRITE (D_UNIT_CONTROL_LOW,
1288                              (GTREGREAD (D_UNIT_CONTROL_LOW) & 0x7F) |
1289                              0x00110000 | tmp_dunit_control_low);
1290        }
1291
1292        /* set SDRAM mode SetCommand 0x1418 */
1293        GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1294        while (GTREGREAD (SDRAM_OPERATION) != 0) {
1295                debug("\n*** SDRAM_OPERATION 1418 after D_UNIT_CONTROL_LOW: Module still busy ... please wait... ***\n");
1296        }
1297
1298/*------------------------------------------------------------------------------ */
1299
1300
1301        /* bank parameters */
1302        /* SDRAM address decode register */
1303        /* program this with the default value */
1304        tmp = 0x02;
1305
1306
1307        debug("drb_size (n*64Mbit): %d\n", info->drb_size);
1308        switch (info->drb_size) {
1309        case 1:         /* 64 Mbit */
1310        case 2:         /* 128 Mbit */
1311                debug("RAM-Device_size 64Mbit or 128Mbit)\n");
1312                tmp |= (0x00 << 4);
1313                break;
1314        case 4:         /* 256 Mbit */
1315        case 8:         /* 512 Mbit */
1316                debug("RAM-Device_size 256Mbit or 512Mbit)\n");
1317                tmp |= (0x01 << 4);
1318                break;
1319        case 16:                /* 1 Gbit */
1320        case 32:                /* 2 Gbit */
1321                debug("RAM-Device_size 1Gbit or 2Gbit)\n");
1322                tmp |= (0x02 << 4);
1323                break;
1324        default:
1325                printf ("Error in dram size calculation\n");
1326                debug("Assume: RAM-Device_size 1Gbit or 2Gbit)\n");
1327                tmp |= (0x02 << 4);
1328                return 1;
1329        }
1330
1331        /* SDRAM bank parameters */
1332        /* the param registers for slot 1 (banks 2+3) are offset by 0x8 */
1333        debug("setting up slot %d config with: %08lx \n", info->slot, tmp);
1334        GT_REG_WRITE (SDRAM_ADDR_CONTROL, tmp);
1335
1336/* ------------------------------------------------------------------------------ */
1337
1338        debug("setting up sdram_timing_control_low with: %08x \n",
1339             0x11511220);
1340        GT_REG_WRITE (SDRAM_TIMING_CONTROL_LOW, 0x11511220);
1341
1342
1343/* ------------------------------------------------------------------------------ */
1344
1345        /* SDRAM configuration */
1346        tmp = GTREGREAD (SDRAM_CONFIG);
1347
1348        if (info->registeredAddrAndControlInputs
1349            || info->registeredDQMBinputs) {
1350                tmp |= (1 << 17);
1351                debug("SPD says: registered Addr. and Cont.: %d; registered DQMBinputs: %d\n",
1352                     info->registeredAddrAndControlInputs,
1353                     info->registeredDQMBinputs);
1354        }
1355
1356        /* Use buffer 1 to return read data to the CPU
1357         * Page 426 MV64360 */
1358        tmp |= (1 << 26);
1359        debug("Before Buffer assignment - sdram_conf: %08x\n",
1360             GTREGREAD (SDRAM_CONFIG));
1361        debug("After Buffer assignment - sdram_conf: %08x\n",
1362             GTREGREAD (SDRAM_CONFIG));
1363
1364        /* SDRAM timing To_do: */
1365
1366
1367        tmp = GTREGREAD (SDRAM_TIMING_CONTROL_HIGH);
1368        debug("# sdram_timing_control_high is : %08lx \n", tmp);
1369
1370        /* SDRAM address decode register */
1371        /* program this with the default value */
1372        tmp = GTREGREAD (SDRAM_ADDR_CONTROL);
1373        debug("SDRAM address control (before: decode): %08x  ",
1374             GTREGREAD (SDRAM_ADDR_CONTROL));
1375        GT_REG_WRITE (SDRAM_ADDR_CONTROL, (tmp | 0x2));
1376        debug("SDRAM address control (after: decode): %08x\n",
1377             GTREGREAD (SDRAM_ADDR_CONTROL));
1378
1379        /* set the SDRAM configuration for each bank */
1380
1381/*      for (i = info->slot * 2; i < ((info->slot * 2) + info->banks); i++) */
1382        {
1383                int l, l1;
1384
1385                i = info->slot;
1386                debug("\n*** Running a MRS cycle for bank %d ***\n", i);
1387
1388                /* map the bank */
1389                memory_map_bank (i, 0, GB / 4);
1390#if 1                           /* test only */
1391
1392                tmp = GTREGREAD (SDRAM_MODE);
1393                GT_REG_WRITE (EXTENDED_DRAM_MODE, 0x0);
1394                GT_REG_WRITE (SDRAM_OPERATION, 0x4);
1395                while (GTREGREAD (SDRAM_OPERATION) != 0) {
1396                        debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
1397                }
1398
1399                GT_REG_WRITE (SDRAM_MODE, tmp | 0x80);
1400                GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1401                while (GTREGREAD (SDRAM_OPERATION) != 0) {
1402                        debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
1403                }
1404                l1 = 0;
1405                for (l=0;l<200;l++)
1406                        l1 += GTREGREAD (SDRAM_OPERATION);
1407
1408                GT_REG_WRITE (SDRAM_MODE, tmp);
1409                GT_REG_WRITE (SDRAM_OPERATION, 0x3);
1410                while (GTREGREAD (SDRAM_OPERATION) != 0) {
1411                        debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
1412                }
1413
1414                /* switch back to normal operation mode */
1415                GT_REG_WRITE (SDRAM_OPERATION, 0x5);
1416                while (GTREGREAD (SDRAM_OPERATION) != 0) {
1417                        debug("\n*** SDRAM_OPERATION 1418 after SDRAM_MODE: Module still busy ... please wait... ***\n");
1418                }
1419
1420#endif /* test only */
1421                /* unmap the bank */
1422                memory_map_bank (i, 0, 0);
1423        }
1424
1425        return 0;
1426}
1427
1428/*
1429 * Check memory range for valid RAM. A simple memory test determines
1430 * the actually available RAM size between addresses `base' and
1431 * `base + maxsize'. Some (not all) hardware errors are detected:
1432 * - short between address lines
1433 * - short between data lines
1434 */
1435long int
1436dram_size(long int *base, long int maxsize)
1437{
1438    volatile long int    *addr, *b=base;
1439    long int     cnt, val, save1, save2;
1440
1441#define STARTVAL (1<<20)        /* start test at 1M */
1442    for (cnt = STARTVAL/sizeof(long); cnt < maxsize/sizeof(long); cnt <<= 1) {
1443            addr = base + cnt;  /* pointer arith! */
1444
1445            save1 = *addr;              /* save contents of addr */
1446            save2 = *b;         /* save contents of base */
1447
1448            *addr=cnt;          /* write cnt to addr */
1449            *b=0;                       /* put null at base */
1450
1451            /* check at base address */
1452            if ((*b) != 0) {
1453                *addr=save1;    /* restore *addr */
1454                *b=save2;       /* restore *b */
1455                return (0);
1456            }
1457            val = *addr;                /* read *addr */
1458            val = *addr;                /* read *addr */
1459
1460            *addr=save1;
1461            *b=save2;
1462
1463            if (val != cnt) {
1464                    debug("Found %08x  at Address %08x (failure)\n", (unsigned int)val, (unsigned int) addr);
1465                    /* fix boundary condition.. STARTVAL means zero */
1466                    if(cnt==STARTVAL/sizeof(long)) cnt=0;
1467                    return (cnt * sizeof(long));
1468            }
1469    }
1470    return maxsize;
1471}
1472
1473#ifdef CONFIG_MV64360_ECC
1474/*
1475 * mv_dma_is_channel_active:
1476 * Checks if a engine is busy.
1477 */
1478int mv_dma_is_channel_active(int engine)
1479{
1480        ulong data;
1481
1482        data = GTREGREAD(MV64360_DMA_CHANNEL0_CONTROL + 4 * engine);
1483        if (data & BIT14)       /* activity status */
1484                return 1;
1485
1486        return 0;
1487}
1488
1489/*
1490 * mv_dma_set_memory_space:
1491 * Set a DMA memory window for the DMA's address decoding map.
1492 */
1493int mv_dma_set_memory_space(ulong mem_space, ulong mem_space_target,
1494                            ulong mem_space_attr, ulong base_address,
1495                            ulong size)
1496{
1497        ulong temp;
1498
1499        /* The base address must be aligned to the size.  */
1500        if (base_address % size != 0)
1501                return 0;
1502
1503        if (size >= 0x10000) {
1504                size &= 0xffff0000;
1505                base_address = (base_address & 0xffff0000);
1506                /* Set the new attributes */
1507                GT_REG_WRITE(MV64360_DMA_BASE_ADDR_REG0 + mem_space * 8,
1508                             (base_address | mem_space_target |
1509                              mem_space_attr));
1510                GT_REG_WRITE((MV64360_DMA_SIZE_REG0 + mem_space * 8),
1511                             (size - 1) & 0xffff0000);
1512                temp = GTREGREAD(MV64360_DMA_BASE_ADDR_ENABLE_REG);
1513                GT_REG_WRITE(DMA_BASE_ADDR_ENABLE_REG,
1514                             (temp & ~(BIT0 << mem_space)));
1515                return 1;
1516        }
1517
1518        return 0;
1519}
1520
1521
1522/*
1523 * mv_dma_transfer:
1524 * Transfer data from source_addr to dest_addr on one of the 4 DMA channels.
1525 */
1526int mv_dma_transfer(int engine, ulong source_addr,
1527                    ulong dest_addr, ulong bytes, ulong command)
1528{
1529        ulong eng_off_reg;      /* Engine Offset Register */
1530
1531        if (bytes > 0xffff)
1532                command = command | BIT31;       /* DMA_16M_DESCRIPTOR_MODE */
1533
1534        command = command | ((command >> 6) & 0x7);
1535        eng_off_reg = engine * 4;
1536        GT_REG_WRITE(MV64360_DMA_CHANNEL0_BYTE_COUNT + eng_off_reg,
1537                     bytes);
1538        GT_REG_WRITE(MV64360_DMA_CHANNEL0_SOURCE_ADDR + eng_off_reg,
1539                     source_addr);
1540        GT_REG_WRITE(MV64360_DMA_CHANNEL0_DESTINATION_ADDR + eng_off_reg,
1541                     dest_addr);
1542        command |= BIT12        /* DMA_CHANNEL_ENABLE */
1543                | BIT9;         /* DMA_NON_CHAIN_MODE */
1544
1545        /* Activate DMA engine By writting to mv_dma_control_register */
1546        GT_REG_WRITE(MV64360_DMA_CHANNEL0_CONTROL + eng_off_reg, command);
1547
1548        return 1;
1549}
1550#endif /* of ifdef CONFIG_MV64360_ECC */
1551
1552/* ppcboot interface function to SDRAM init - this is where all the
1553 * controlling logic happens */
1554phys_size_t
1555initdram(int board_type)
1556{
1557        int checkbank[4] = { [0 ... 3] = 0 };
1558        ulong realsize, total, check;
1559        AUX_MEM_DIMM_INFO dimmInfo1;
1560        AUX_MEM_DIMM_INFO dimmInfo2;
1561        int bank_no, nhr;
1562#ifdef CONFIG_MV64360_ECC
1563        ulong dest, mem_space_attr;
1564#endif /* of ifdef CONFIG_MV64360_ECC */
1565
1566        /* first, use the SPD to get info about the SDRAM/ DDRRAM */
1567
1568        /* check the NHR bit and skip mem init if it's already done */
1569        nhr = get_hid0() & (1 << 16);
1570
1571        if (nhr) {
1572                printf("Skipping SD- DDRRAM setup due to NHR bit being set\n");
1573        } else {
1574                /* DIMM0 */
1575                (void)check_dimm(0, &dimmInfo1);
1576
1577                /* DIMM1 */
1578                (void)check_dimm(1, &dimmInfo2);
1579
1580                memory_map_bank(0, 0, 0);
1581                memory_map_bank(1, 0, 0);
1582                memory_map_bank(2, 0, 0);
1583                memory_map_bank(3, 0, 0);
1584
1585                if (dimmInfo1.numOfModuleBanks && setup_sdram(&dimmInfo1)) {
1586                        printf("Setup for DIMM1 failed.\n");
1587                }
1588
1589                if (dimmInfo2.numOfModuleBanks && setup_sdram(&dimmInfo2)) {
1590                        printf("Setup for DIMM2 failed.\n");
1591                }
1592
1593                /* set the NHR bit */
1594                set_hid0(get_hid0() | (1 << 16));
1595        }
1596        /* next, size the SDRAM banks */
1597
1598        realsize = total = 0;
1599        check = GB/4;
1600        if (dimmInfo1.numOfModuleBanks > 0) {checkbank[0] = 1; printf("-- DIMM1 has 1 bank\n");}
1601        if (dimmInfo1.numOfModuleBanks > 1) {checkbank[1] = 1; printf("-- DIMM1 has 2 banks\n");}
1602        if (dimmInfo1.numOfModuleBanks > 2)
1603                printf("Error, SPD claims DIMM1 has >2 banks\n");
1604
1605        if (dimmInfo2.numOfModuleBanks > 0) {checkbank[2] = 1; printf("-- DIMM2 has 1 bank\n");}
1606        if (dimmInfo2.numOfModuleBanks > 1) {checkbank[3] = 1; printf("-- DIMM2 has 2 banks\n");}
1607        if (dimmInfo2.numOfModuleBanks > 2)
1608                printf("Error, SPD claims DIMM2 has >2 banks\n");
1609
1610        for (bank_no = 0; bank_no < CONFIG_SYS_DRAM_BANKS; bank_no++) {
1611                /* skip over banks that are not populated */
1612                if (! checkbank[bank_no])
1613                        continue;
1614
1615                if ((total + check) > CONFIG_SYS_GT_REGS)
1616                        check = CONFIG_SYS_GT_REGS - total;
1617
1618                memory_map_bank(bank_no, total, check);
1619                realsize = dram_size((long int *)total, check);
1620                memory_map_bank(bank_no, total, realsize);
1621
1622#ifdef CONFIG_MV64360_ECC
1623                if (((dimmInfo1.errorCheckType != 0) &&
1624                     ((dimmInfo2.errorCheckType != 0) ||
1625                      (dimmInfo2.numOfModuleBanks == 0))) &&
1626                    (CPCI750_ECC_TEST)) {
1627                        printf("ECC Initialization of Bank %d:", bank_no);
1628                        mem_space_attr = ((~(BIT0 << bank_no)) & 0xf) << 8;
1629                        mv_dma_set_memory_space(0, 0, mem_space_attr, total,
1630                                                realsize);
1631                        for (dest = total; dest < total + realsize;
1632                             dest += _8M) {
1633                                mv_dma_transfer(0, total, dest, _8M,
1634                                                BIT8 |  /* DMA_DTL_128BYTES */
1635                                                BIT3 |  /* DMA_HOLD_SOURCE_ADDR */
1636                                                BIT11); /* DMA_BLOCK_TRANSFER_MODE */
1637                                while (mv_dma_is_channel_active(0))
1638                                        ;
1639                        }
1640                        printf(" PASS\n");
1641                }
1642#endif /* of ifdef CONFIG_MV64360_ECC */
1643
1644                total += realsize;
1645        }
1646
1647/*      Setup Ethernet DMA Adress window to DRAM Area */
1648        return(total);
1649}
1650
1651/* ***************************************************************************************
1652! *                             SDRAM INIT                                              *
1653! *  This procedure detect all Sdram types: 64, 128, 256, 512 Mbit, 1Gbit and 2Gb       *
1654! *               This procedure fits only the Atlantis                                *
1655! *                                                                                     *
1656! *************************************************************************************** */
1657
1658
1659/* ***************************************************************************************
1660! *                             DFCDL initialize MV643xx Design Considerations             *
1661! *                                                                                     *
1662! *************************************************************************************** */
1663int set_dfcdlInit (void)
1664{
1665        int i;
1666        unsigned int dfcdl_word = 0x0000014f;
1667
1668        for (i = 0; i < 64; i++) {
1669                GT_REG_WRITE (SRAM_DATA0, dfcdl_word);
1670        }
1671        GT_REG_WRITE (DFCDL_CONFIG0, 0x00300000);       /* enable dynamic delay line updating */
1672
1673
1674        return (0);
1675}
1676
1677int do_show_ecc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
1678{
1679        unsigned int ecc_counter;
1680        unsigned int ecc_addr;
1681
1682        GT_REG_READ(0x1458, &ecc_counter);
1683        GT_REG_READ(0x1450, &ecc_addr);
1684        GT_REG_WRITE(0x1450, 0);
1685
1686        printf("Error Counter since Reset:  %8d\n", ecc_counter);
1687        printf("Last error address       :0x%08x (" , ecc_addr & 0xfffffff8);
1688        if (ecc_addr & 0x01)
1689                printf("double");
1690        else
1691                printf("single");
1692        printf(" bit) at DDR-RAM CS#%d\n", ((ecc_addr & 0x6) >> 1));
1693
1694        return 0;
1695}
1696
1697
1698U_BOOT_CMD(
1699        show_ecc, 1, 1, do_show_ecc,
1700        "Show Marvell MV64360 ECC Info",
1701        "Show Marvell MV64360 ECC Counter and last error."
1702);
1703