LXR uboot/board/freescale/mpc8360erdk/nand.c

   1/*
   2 * MPC8360E-RDK support for the NAND on FSL UPM
   3 *
   4 * Copyright (C) 2007 MontaVista Software, Inc.
   5 *                    Anton Vorontsov <avorontsov@ru.mvista.com>
   6 *
   7 * SPDX-License-Identifier:     GPL-2.0+
   8 */
   9
  10#include <config.h>
  11#include <common.h>
  12#include <asm/io.h>
  13#include <asm/immap_83xx.h>
  14#include <linux/mtd/mtd.h>
  15#include <linux/mtd/fsl_upm.h>
  16#include <nand.h>
  17
  18static struct immap *im = (struct immap *)CONFIG_SYS_IMMR;
  19
  20static const u32 upm_array[] = {
  21        0x0ff03c30, 0x0ff03c30, 0x0ff03c34, 0x0ff33c30, /* Words  0 to  3 */
  22        0xfff33c31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words  4 to  7 */
  23        0x0faf3c30, 0x0faf3c30, 0x0faf3c30, 0x0fff3c34, /* Words  8 to 11 */
  24        0xffff3c31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 12 to 15 */
  25        0x0fa3fc30, 0x0fa3fc30, 0x0fa3fc30, 0x0ff3fc34, /* Words 16 to 19 */
  26        0xfff3fc31, 0xfffffc30, 0xfffffc30, 0xfffffc30, /* Words 20 to 23 */
  27        0x0ff33c30, 0x0fa33c30, 0x0fa33c34, 0x0ff33c30, /* Words 24 to 27 */
  28        0xfff33c31, 0xfff0fc30, 0xfff0fc30, 0xfff0fc30, /* Words 28 to 31 */
  29        0xfff3fc30, 0xfff3fc30, 0xfff6fc30, 0xfffcfc30, /* Words 32 to 35 */
  30        0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, /* Words 36 to 39 */
  31        0xfffcfc30, 0xfffcfc30, 0xfffcfc30, 0xfffcfc30, /* Words 40 to 43 */
  32        0xfffdfc30, 0xfffffc30, 0xfffffc30, 0xfffffc31, /* Words 44 to 47 */
  33        0xfffffc30, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 48 to 51 */
  34        0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, /* Words 52 to 55 */
  35        0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 56 to 59 */
  36        0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, /* Words 60 to 63 */
  37};
  38
  39static void upm_setup(struct fsl_upm *upm)
  40{
  41        int i;
  42
  43        /* write upm array */
  44        out_be32(upm->mxmr, MxMR_OP_WARR);
  45
  46        for (i = 0; i < 64; i++) {
  47                out_be32(upm->mdr, upm_array[i]);
  48                out_8(upm->io_addr, 0x0);
  49        }
  50
  51        /* normal operation */
  52        out_be32(upm->mxmr, MxMR_OP_NORM);
  53        while (in_be32(upm->mxmr) != MxMR_OP_NORM)
  54                eieio();
  55}
  56
  57static int dev_ready(int chip_nr)
  58{
  59        if (in_be32(&im->qepio.ioport[4].pdat) & 0x00002000) {
  60                debug("nand ready\n");
  61                return 1;
  62        }
  63
  64        debug("nand busy\n");
  65        return 0;
  66}
  67
  68static struct fsl_upm_nand fun = {
  69        .upm = {
  70                .io_addr = (void *)CONFIG_SYS_NAND_BASE,
  71        },
  72        .width = 8,
  73        .upm_cmd_offset = 8,
  74        .upm_addr_offset = 16,
  75        .dev_ready = dev_ready,
  76        .wait_flags = FSL_UPM_WAIT_RUN_PATTERN,
  77        .chip_delay = 50,
  78};
  79
  80int board_nand_init(struct nand_chip *nand)
  81{
  82        fun.upm.mxmr = &im->im_lbc.mamr;
  83        fun.upm.mdr = &im->im_lbc.mdr;
  84        fun.upm.mar = &im->im_lbc.mar;
  85
  86        upm_setup(&fun.upm);
  87
  88        return fsl_upm_nand_init(nand, &fun);
  89}
  90