1/* 2 * (C) Copyright 2009 3 * Marvell Semiconductor <www.marvell.com> 4 * Written-by: Prafulla Wadaskar <prafulla@marvell.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9#include <common.h> 10#include <asm/io.h> 11#include <asm/arch/kirkwood.h> 12#include <nand.h> 13 14/* NAND Flash Soc registers */ 15struct kwnandf_registers { 16 u32 rd_params; /* 0x10418 */ 17 u32 wr_param; /* 0x1041c */ 18 u8 pad[0x10470 - 0x1041c - 4]; 19 u32 ctrl; /* 0x10470 */ 20}; 21 22static struct kwnandf_registers *nf_reg = 23 (struct kwnandf_registers *)KW_NANDF_BASE; 24 25/* 26 * hardware specific access to control-lines/bits 27 */ 28#define NAND_ACTCEBOOT_BIT 0x02 29 30static void kw_nand_hwcontrol(struct mtd_info *mtd, int cmd, 31 unsigned int ctrl) 32{ 33 struct nand_chip *nc = mtd->priv; 34 u32 offs; 35 36 if (cmd == NAND_CMD_NONE) 37 return; 38 39 if (ctrl & NAND_CLE) 40 offs = (1 << 0); /* Commands with A[1:0] == 01 */ 41 else if (ctrl & NAND_ALE) 42 offs = (1 << 1); /* Addresses with A[1:0] == 10 */ 43 else 44 return; 45 46 writeb(cmd, nc->IO_ADDR_W + offs); 47} 48 49void kw_nand_select_chip(struct mtd_info *mtd, int chip) 50{ 51 u32 data; 52 53 data = readl(&nf_reg->ctrl); 54 data |= NAND_ACTCEBOOT_BIT; 55 writel(data, &nf_reg->ctrl); 56} 57 58int board_nand_init(struct nand_chip *nand) 59{ 60 nand->options = NAND_COPYBACK | NAND_CACHEPRG | NAND_NO_PADDING; 61#if defined(CONFIG_SYS_NAND_NO_SUBPAGE_WRITE) 62 nand->options |= NAND_NO_SUBPAGE_WRITE; 63#endif 64#if defined(CONFIG_NAND_ECC_BCH) 65 nand->ecc.mode = NAND_ECC_SOFT_BCH; 66#else 67 nand->ecc.mode = NAND_ECC_SOFT; 68#endif 69 nand->cmd_ctrl = kw_nand_hwcontrol; 70 nand->chip_delay = 40; 71 nand->select_chip = kw_nand_select_chip; 72 return 0; 73} 74