LXR uboot/drivers/spi/tegra20

   1/*
   2 * NVIDIA Tegra SPI-SLINK controller
   3 *
   4 * Copyright (c) 2010-2013 NVIDIA Corporation
   5 *
   6 * See file CREDITS for list of people who contributed to this
   7 * project.
   8 *
   9 * This software is licensed under the terms of the GNU General Public
  10 * License version 2, as published by the Free Software Foundation, and
  11 * may be copied, distributed, and modified under those terms.
  12 *
  13 * This program is distributed in the hope that it will be useful,
  14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16 * GNU General Public License for more details.
  17 *
  18 * You should have received a copy of the GNU General Public License
  19 * along with this program; if not, write to the Free Software
  20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21 * MA 02111-1307 USA
  22 */
  23
  24#include <common.h>
  25#include <malloc.h>
  26#include <asm/io.h>
  27#include <asm/gpio.h>
  28#include <asm/arch/clock.h>
  29#include <asm/arch-tegra/clk_rst.h>
  30#include <asm/arch-tegra20/tegra20_slink.h>
  31#include <spi.h>
  32#include <fdtdec.h>
  33
  34DECLARE_GLOBAL_DATA_PTR;
  35
  36/* COMMAND */
  37#define SLINK_CMD_ENB                   (1 << 31)
  38#define SLINK_CMD_GO                    (1 << 30)
  39#define SLINK_CMD_M_S                   (1 << 28)
  40#define SLINK_CMD_CK_SDA                (1 << 21)
  41#define SLINK_CMD_CS_POL                (1 << 13)
  42#define SLINK_CMD_CS_VAL                (1 << 12)
  43#define SLINK_CMD_CS_SOFT               (1 << 11)
  44#define SLINK_CMD_BIT_LENGTH            (1 << 4)
  45#define SLINK_CMD_BIT_LENGTH_MASK       0x0000001F
  46/* COMMAND2 */
  47#define SLINK_CMD2_TXEN                 (1 << 30)
  48#define SLINK_CMD2_RXEN                 (1 << 31)
  49#define SLINK_CMD2_SS_EN                (1 << 18)
  50#define SLINK_CMD2_SS_EN_SHIFT          18
  51#define SLINK_CMD2_SS_EN_MASK           0x000C0000
  52#define SLINK_CMD2_CS_ACTIVE_BETWEEN    (1 << 17)
  53/* STATUS */
  54#define SLINK_STAT_BSY                  (1 << 31)
  55#define SLINK_STAT_RDY                  (1 << 30)
  56#define SLINK_STAT_ERR                  (1 << 29)
  57#define SLINK_STAT_RXF_FLUSH            (1 << 27)
  58#define SLINK_STAT_TXF_FLUSH            (1 << 26)
  59#define SLINK_STAT_RXF_OVF              (1 << 25)
  60#define SLINK_STAT_TXF_UNR              (1 << 24)
  61#define SLINK_STAT_RXF_EMPTY            (1 << 23)
  62#define SLINK_STAT_RXF_FULL             (1 << 22)
  63#define SLINK_STAT_TXF_EMPTY            (1 << 21)
  64#define SLINK_STAT_TXF_FULL             (1 << 20)
  65#define SLINK_STAT_TXF_OVF              (1 << 19)
  66#define SLINK_STAT_RXF_UNR              (1 << 18)
  67#define SLINK_STAT_CUR_BLKCNT           (1 << 15)
  68/* STATUS2 */
  69#define SLINK_STAT2_RXF_FULL_CNT        (1 << 16)
  70#define SLINK_STAT2_TXF_FULL_CNT        (1 << 0)
  71
  72#define SPI_TIMEOUT             1000
  73#define TEGRA_SPI_MAX_FREQ      52000000
  74
  75struct spi_regs {
  76        u32 command;    /* SLINK_COMMAND_0 register  */
  77        u32 command2;   /* SLINK_COMMAND2_0 reg */
  78        u32 status;     /* SLINK_STATUS_0 register */
  79        u32 reserved;   /* Reserved offset 0C */
  80        u32 mas_data;   /* SLINK_MAS_DATA_0 reg */
  81        u32 slav_data;  /* SLINK_SLAVE_DATA_0 reg */
  82        u32 dma_ctl;    /* SLINK_DMA_CTL_0 register */
  83        u32 status2;    /* SLINK_STATUS2_0 reg */
  84        u32 rsvd[56];   /* 0x20 to 0xFF reserved */
  85        u32 tx_fifo;    /* SLINK_TX_FIFO_0 reg off 100h */
  86        u32 rsvd2[31];  /* 0x104 to 0x17F reserved */
  87        u32 rx_fifo;    /* SLINK_RX_FIFO_0 reg off 180h */
  88};
  89
  90struct tegra_spi_ctrl {
  91        struct spi_regs *regs;
  92        unsigned int freq;
  93        unsigned int mode;
  94        int periph_id;
  95        int valid;
  96};
  97
  98struct tegra_spi_slave {
  99        struct spi_slave slave;
 100        struct tegra_spi_ctrl *ctrl;
 101};
 102
 103static struct tegra_spi_ctrl spi_ctrls[CONFIG_TEGRA_SLINK_CTRLS];
 104
 105static inline struct tegra_spi_slave *to_tegra_spi(struct spi_slave *slave)
 106{
 107        return container_of(slave, struct tegra_spi_slave, slave);
 108}
 109
 110int tegra30_spi_cs_is_valid(unsigned int bus, unsigned int cs)
 111{
 112        if (bus >= CONFIG_TEGRA_SLINK_CTRLS || cs > 3 || !spi_ctrls[bus].valid)
 113                return 0;
 114        else
 115                return 1;
 116}
 117
 118struct spi_slave *tegra30_spi_setup_slave(unsigned int bus, unsigned int cs,
 119                unsigned int max_hz, unsigned int mode)
 120{
 121        struct tegra_spi_slave *spi;
 122
 123        debug("%s: bus: %u, cs: %u, max_hz: %u, mode: %u\n", __func__,
 124                bus, cs, max_hz, mode);
 125
 126        if (!spi_cs_is_valid(bus, cs)) {
 127                printf("SPI error: unsupported bus %d / chip select %d\n",
 128                       bus, cs);
 129                return NULL;
 130        }
 131
 132        if (max_hz > TEGRA_SPI_MAX_FREQ) {
 133                printf("SPI error: unsupported frequency %d Hz. Max frequency"
 134                        " is %d Hz\n", max_hz, TEGRA_SPI_MAX_FREQ);
 135                return NULL;
 136        }
 137
 138        spi = spi_alloc_slave(struct tegra_spi_slave, bus, cs);
 139        if (!spi) {
 140                printf("SPI error: malloc of SPI structure failed\n");
 141                return NULL;
 142        }
 143        spi->ctrl = &spi_ctrls[bus];
 144        if (!spi->ctrl) {
 145                printf("SPI error: could not find controller for bus %d\n",
 146                       bus);
 147                return NULL;
 148        }
 149
 150        if (max_hz < spi->ctrl->freq) {
 151                debug("%s: limiting frequency from %u to %u\n", __func__,
 152                      spi->ctrl->freq, max_hz);
 153                spi->ctrl->freq = max_hz;
 154        }
 155        spi->ctrl->mode = mode;
 156
 157        return &spi->slave;
 158}
 159
 160void tegra30_spi_free_slave(struct spi_slave *slave)
 161{
 162        struct tegra_spi_slave *spi = to_tegra_spi(slave);
 163
 164        free(spi);
 165}
 166
 167int tegra30_spi_init(int *node_list, int count)
 168{
 169        struct tegra_spi_ctrl *ctrl;
 170        int i;
 171        int node = 0;
 172        int found = 0;
 173
 174        for (i = 0; i < count; i++) {
 175                ctrl = &spi_ctrls[i];
 176                node = node_list[i];
 177
 178                ctrl->regs = (struct spi_regs *)fdtdec_get_addr(gd->fdt_blob,
 179                                                                node, "reg");
 180                if ((fdt_addr_t)ctrl->regs == FDT_ADDR_T_NONE) {
 181                        debug("%s: no slink register found\n", __func__);
 182                        continue;
 183                }
 184                ctrl->freq = fdtdec_get_int(gd->fdt_blob, node,
 185                                            "spi-max-frequency", 0);
 186                if (!ctrl->freq) {
 187                        debug("%s: no slink max frequency found\n", __func__);
 188                        continue;
 189                }
 190
 191                ctrl->periph_id = clock_decode_periph_id(gd->fdt_blob, node);
 192                if (ctrl->periph_id == PERIPH_ID_NONE) {
 193                        debug("%s: could not decode periph id\n", __func__);
 194                        continue;
 195                }
 196                ctrl->valid = 1;
 197                found = 1;
 198
 199                debug("%s: found controller at %p, freq = %u, periph_id = %d\n",
 200                      __func__, ctrl->regs, ctrl->freq, ctrl->periph_id);
 201        }
 202        return !found;
 203}
 204
 205int tegra30_spi_claim_bus(struct spi_slave *slave)
 206{
 207        struct tegra_spi_slave *spi = to_tegra_spi(slave);
 208        struct spi_regs *regs = spi->ctrl->regs;
 209        u32 reg;
 210
 211        /* Change SPI clock to correct frequency, PLLP_OUT0 source */
 212        clock_start_periph_pll(spi->ctrl->periph_id, CLOCK_ID_PERIPH,
 213                               spi->ctrl->freq);
 214
 215        /* Clear stale status here */
 216        reg = SLINK_STAT_RDY | SLINK_STAT_RXF_FLUSH | SLINK_STAT_TXF_FLUSH | \
 217                SLINK_STAT_RXF_UNR | SLINK_STAT_TXF_OVF;
 218        writel(reg, &regs->status);
 219        debug("%s: STATUS = %08x\n", __func__, readl(&regs->status));
 220
 221        /* Set master mode and sw controlled CS */
 222        reg = readl(&regs->command);
 223        reg |= SLINK_CMD_M_S | SLINK_CMD_CS_SOFT;
 224        writel(reg, &regs->command);
 225        debug("%s: COMMAND = %08x\n", __func__, readl(&regs->command));
 226
 227        return 0;
 228}
 229
 230void tegra30_spi_cs_activate(struct spi_slave *slave)
 231{
 232        struct tegra_spi_slave *spi = to_tegra_spi(slave);
 233        struct spi_regs *regs = spi->ctrl->regs;
 234
 235        /* CS is negated on Tegra, so drive a 1 to get a 0 */
 236        setbits_le32(&regs->command, SLINK_CMD_CS_VAL);
 237}
 238
 239void tegra30_spi_cs_deactivate(struct spi_slave *slave)
 240{
 241        struct tegra_spi_slave *spi = to_tegra_spi(slave);
 242        struct spi_regs *regs = spi->ctrl->regs;
 243
 244        /* CS is negated on Tegra, so drive a 0 to get a 1 */
 245        clrbits_le32(&regs->command, SLINK_CMD_CS_VAL);
 246}
 247
 248int tegra30_spi_xfer(struct spi_slave *slave, unsigned int bitlen,
 249                const void *data_out, void *data_in, unsigned long flags)
 250{
 251        struct tegra_spi_slave *spi = to_tegra_spi(slave);
 252        struct spi_regs *regs = spi->ctrl->regs;
 253        u32 reg, tmpdout, tmpdin = 0;
 254        const u8 *dout = data_out;
 255        u8 *din = data_in;
 256        int num_bytes;
 257        int ret;
 258
 259        debug("%s: slave %u:%u dout %p din %p bitlen %u\n",
 260              __func__, slave->bus, slave->cs, dout, din, bitlen);
 261        if (bitlen % 8)
 262                return -1;
 263        num_bytes = bitlen / 8;
 264
 265        ret = 0;
 266
 267        reg = readl(&regs->status);
 268        writel(reg, &regs->status);     /* Clear all SPI events via R/W */
 269        debug("%s entry: STATUS = %08x\n", __func__, reg);
 270
 271        reg = readl(&regs->status2);
 272        writel(reg, &regs->status2);    /* Clear all STATUS2 events via R/W */
 273        debug("%s entry: STATUS2 = %08x\n", __func__, reg);
 274
 275        debug("%s entry: COMMAND = %08x\n", __func__, readl(&regs->command));
 276
 277        clrsetbits_le32(&regs->command2, SLINK_CMD2_SS_EN_MASK,
 278                        SLINK_CMD2_TXEN | SLINK_CMD2_RXEN |
 279                        (slave->cs << SLINK_CMD2_SS_EN_SHIFT));
 280        debug("%s entry: COMMAND2 = %08x\n", __func__, readl(&regs->command2));
 281
 282        if (flags & SPI_XFER_BEGIN)
 283                spi_cs_activate(slave);
 284
 285        /* handle data in 32-bit chunks */
 286        while (num_bytes > 0) {
 287                int bytes;
 288                int is_read = 0;
 289                int tm, i;
 290
 291                tmpdout = 0;
 292                bytes = (num_bytes > 4) ?  4 : num_bytes;
 293
 294                if (dout != NULL) {
 295                        for (i = 0; i < bytes; ++i)
 296                                tmpdout = (tmpdout << 8) | dout[i];
 297                        dout += bytes;
 298                }
 299
 300                num_bytes -= bytes;
 301
 302                clrsetbits_le32(&regs->command, SLINK_CMD_BIT_LENGTH_MASK,
 303                                bytes * 8 - 1);
 304                writel(tmpdout, &regs->tx_fifo);
 305                setbits_le32(&regs->command, SLINK_CMD_GO);
 306
 307                /*
 308                 * Wait for SPI transmit FIFO to empty, or to time out.
 309                 * The RX FIFO status will be read and cleared last
 310                 */
 311                for (tm = 0, is_read = 0; tm < SPI_TIMEOUT; ++tm) {
 312                        u32 status;
 313
 314                        status = readl(&regs->status);
 315
 316                        /* We can exit when we've had both RX and TX activity */
 317                        if (is_read && (status & SLINK_STAT_TXF_EMPTY))
 318                                break;
 319
 320                        if ((status & (SLINK_STAT_BSY | SLINK_STAT_RDY)) !=
 321                                        SLINK_STAT_RDY)
 322                                tm++;
 323
 324                        else if (!(status & SLINK_STAT_RXF_EMPTY)) {
 325                                tmpdin = readl(&regs->rx_fifo);
 326                                is_read = 1;
 327
 328                                /* swap bytes read in */
 329                                if (din != NULL) {
 330                                        for (i = bytes - 1; i >= 0; --i) {
 331                                                din[i] = tmpdin & 0xff;
 332                                                tmpdin >>= 8;
 333                                        }
 334                                        din += bytes;
 335                                }
 336                        }
 337                }
 338
 339                if (tm >= SPI_TIMEOUT)
 340                        ret = tm;
 341
 342                /* clear ACK RDY, etc. bits */
 343                writel(readl(&regs->status), &regs->status);
 344        }
 345
 346        if (flags & SPI_XFER_END)
 347                spi_cs_deactivate(slave);
 348
 349        debug("%s: transfer ended. Value=%08x, status = %08x\n",
 350              __func__, tmpdin, readl(&regs->status));
 351
 352        if (ret) {
 353                printf("%s: timeout during SPI transfer, tm %d\n",
 354                       __func__, ret);
 355                return -1;
 356        }
 357
 358        return 0;
 359}
 360