1
2
3
4
5
6
7
8
9
10
11
12
13
14#ifndef __CONFIG_H
15#define __CONFIG_H
16
17
18
19
20
21
22#define CONFIG_MPC855 1
23#define CONFIG_KUP4K 1
24
25#define CONFIG_SYS_TEXT_BASE 0x40000000
26
27#define CONFIG_8xx_CONS_SMC1 1
28#undef CONFIG_8xx_CONS_SMC2
29#undef CONFIG_8xx_CONS_NONE
30#define CONFIG_BAUDRATE 115200
31#define CONFIG_BOOTDELAY 1
32
33#define CONFIG_BOARD_TYPES 1
34
35#undef CONFIG_BOOTARGS
36
37#define CONFIG_EXTRA_ENV_SETTINGS \
38"slot_a_boot=setenv bootargs root=/dev/sda2 ip=off;" \
39 "run addhw; mw.b 400000 00 80; diskboot 400000 0:1; bootm 400000\0" \
40"slot_b_boot=setenv bootargs root=/dev/sda2 ip=off;" \
41 "run addhw; mw.b 400000 00 80; diskboot 400000 2:1; bootm 400000\0" \
42"nfs_boot=mw.b 400000 00 80; dhcp; run nfsargs addip addhw; bootm 400000\0" \
43"fat_boot=mw.b 400000 00 80; fatload ide 2:1 400000 st.bin; run addhw; \
44 bootm 400000 \0" \
45"panic_boot=echo No Bootdevice !!! reset\0" \
46"nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${rootpath}\0" \
47"ramargs=setenv bootargs root=/dev/ram rw\0" \
48"addip=setenv bootargs ${bootargs} ip=${ipaddr}::${gatewayip}" \
49 ":${netmask}:${hostname}:${netdev}:off\0" \
50"addhw=setenv bootargs ${bootargs} ${mtdparts} console=${console} ${debug} \
51 hw=${hw} key1=${key1} panic=1 mem=${mem}\0" \
52"console=ttyCPM0,115200\0" \
53"netdev=eth0\0" \
54"contrast=20\0" \
55"silent=1\0" \
56"mtdparts=" MTDPARTS_DEFAULT "\0" \
57"load=tftp 200000 bootloader-4k.bitmap;tftp 100000 bootloader-4k.bin\0" \
58"update=protect off 1:0-9;era 1:0-9;cp.b 100000 40000000 ${filesize};" \
59 "cp.b 200000 40050000 14000\0"
60
61#define CONFIG_BOOTCOMMAND \
62 "run fat_boot;run slot_b_boot;run slot_a_boot;run nfs_boot;run panic_boot"
63
64#define CONFIG_PREBOOT "setenv preboot; saveenv"
65
66#define CONFIG_MISC_INIT_R 1
67#define CONFIG_MISC_INIT_F 1
68
69#define CONFIG_LOADS_ECHO 1
70#undef CONFIG_SYS_LOADS_BAUD_CHANGE
71
72#define CONFIG_WATCHDOG 1
73
74#define CONFIG_STATUS_LED 1
75
76#undef CONFIG_CAN_DRIVER
77
78
79
80
81#define CONFIG_BOOTP_SUBNETMASK
82#define CONFIG_BOOTP_GATEWAY
83#define CONFIG_BOOTP_HOSTNAME
84#define CONFIG_BOOTP_BOOTPATH
85#define CONFIG_BOOTP_BOOTFILESIZE
86
87#define CONFIG_MAC_PARTITION
88#define CONFIG_DOS_PARTITION
89
90
91
92
93#define CONFIG_SYS_I2C
94#define CONFIG_SYS_I2C_SOFT
95#define CONFIG_SYS_I2C_SOFT_SPEED 93000
96#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
97
98
99
100
101#define PB_SCL 0x00000020
102#define PB_SDA 0x00000010
103
104#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL)
105#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA)
106#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
107#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
108#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \
109 else immr->im_cpm.cp_pbdat &= ~PB_SDA
110#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \
111 else immr->im_cpm.cp_pbdat &= ~PB_SCL
112#define I2C_DELAY udelay(2)
113
114
115
116
117
118#define CONFIG_SYS_I2C_PICIO_ADDR 0x21
119#define CONFIG_SYS_I2C_RTC_ADDR 0x51
120
121
122
123#define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_PICIO_ADDR, \
124 CONFIG_SYS_I2C_RTC_ADDR, \
125 }
126
127#define CONFIG_RTC_PCF8563
128
129#define CONFIG_SYS_DISCOVER_PHY
130#define CONFIG_MII
131
132
133#define CONFIG_ENV_OVERWRITE
134
135
136
137
138#include <config_cmd_default.h>
139
140#define CONFIG_CMD_DATE
141#define CONFIG_CMD_DHCP
142#define CONFIG_CMD_I2C
143#define CONFIG_CMD_IDE
144#define CONFIG_CMD_MII
145#define CONFIG_CMD_NFS
146#define CONFIG_CMD_FAT
147#define CONFIG_CMD_SNTP
148
149#ifdef CONFIG_POST
150 #define CONFIG_CMD_DIAG
151#endif
152
153
154
155
156#define CONFIG_SYS_LONGHELP
157#if defined(CONFIG_CMD_KGDB)
158#define CONFIG_SYS_CBSIZE 1024
159#else
160#define CONFIG_SYS_CBSIZE 512
161#endif
162
163#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
164#define CONFIG_SYS_MAXARGS 16
165#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
166
167#define CONFIG_SYS_MEMTEST_START 0x000400000
168#define CONFIG_SYS_MEMTEST_END 0x005C00000
169#define CONFIG_SYS_ALT_MEMTEST 1
170#define CONFIG_SYS_MEMTEST_SCRATCH 0x90000200
171
172#define CONFIG_SYS_LOAD_ADDR 0x400000
173
174#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 115200 }
175
176#define CONFIG_SYS_CONSOLE_INFO_QUIET 1
177
178
179
180
181
182
183
184
185
186#define CONFIG_SYS_IMMR 0xFFF00000
187
188
189
190
191#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
192#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00
193#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
194#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
195
196
197
198
199
200
201#define CONFIG_SYS_SDRAM_BASE 0x00000000
202#define CONFIG_SYS_FLASH_BASE 0x40000000
203#define CONFIG_SYS_MONITOR_LEN (192 << 10)
204#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
205#define CONFIG_SYS_MALLOC_LEN (128 << 10)
206
207
208
209
210
211
212#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
213
214
215
216
217#define CONFIG_SYS_MAX_FLASH_BANKS 1
218#define CONFIG_SYS_MAX_FLASH_SECT 19
219
220#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
221#define CONFIG_SYS_FLASH_WRITE_TOUT 500
222
223#define CONFIG_ENV_IS_IN_FLASH 1
224#define CONFIG_ENV_OFFSET 0x40000
225#define CONFIG_ENV_SIZE 0x1000
226#define CONFIG_ENV_SECT_SIZE 0x10000
227
228
229
230
231#define MTDPARTS_DEFAULT "mtdparts=40000000.flash:256k(u-boot)," \
232 "64k(env)," \
233 "128k(splash)," \
234 "512k(etc)," \
235 "64k(hw-info)"
236
237
238
239
240#define CONFIG_SYS_HWINFO_OFFSET 0x000F0000
241#define CONFIG_SYS_HWINFO_SIZE 0x00000100
242#define CONFIG_SYS_HWINFO_MAGIC 0x4B26500D
243
244
245
246
247#define CONFIG_SYS_CACHELINE_SIZE 16
248#if defined(CONFIG_CMD_KGDB)
249#define CONFIG_SYS_CACHELINE_SHIFT 4
250#endif
251
252
253
254
255
256
257
258#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
259
260
261
262
263
264
265#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00)
266
267
268
269
270
271
272#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
273
274
275
276
277
278#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
279
280
281
282
283
284
285#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
286
287
288
289
290
291
292
293
294
295#define CONFIG_SYS_PLPRCR ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
296
297
298
299
300
301
302
303#define SCCR_MASK SCCR_EBDF00
304#define CONFIG_SYS_SCCR (SCCR_TBS | SCCR_EBDF01 | \
305 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
306 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
307 SCCR_DFALCD00)
308
309
310
311
312
313
314
315
316#define CONFIG_PCMCIA_SLOT_A 1
317
318#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
319#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
320#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
321#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
322#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
323#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
324#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
325#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
326
327#define PCMCIA_SOCKETS_NO 2
328#define PCMCIA_MEM_WIN_NO 8
329
330
331
332
333
334#define CONFIG_IDE_PREINIT 1
335#define CONFIG_IDE_8xx_PCCARD 1
336
337#undef CONFIG_IDE_8xx_DIRECT
338#define CONFIG_IDE_LED 1
339#undef CONFIG_IDE_RESET
340
341#define CONFIG_SYS_IDE_MAXBUS 2
342#define CONFIG_SYS_IDE_MAXDEVICE 4
343
344#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
345
346#define CONFIG_SYS_ATA_IDE1_OFFSET (4 * CONFIG_SYS_PCMCIA_MEM_SIZE)
347
348#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR
349
350
351#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
352
353
354#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
355
356
357#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100
358
359
360
361
362
363
364#define CONFIG_SYS_DER 0
365
366
367
368
369
370
371#define FLASH_BASE0_PRELIM 0x40000000
372
373
374
375
376
377#define CONFIG_SYS_REMAP_OR_AM 0x80000000
378#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000
379
380
381
382
383#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV2 | OR_CSNT_SAM | \
384 OR_SCY_5_CLK | OR_EHTR | OR_BI)
385
386#define CONFIG_SYS_OR0_REMAP \
387 (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
388#define CONFIG_SYS_OR0_PRELIM \
389 (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
390#define CONFIG_SYS_BR0_PRELIM \
391 ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
392
393
394
395#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423#if defined(CONFIG_80MHz)
424#define CONFIG_SYS_MAMR_PTA 156
425#elif defined(CONFIG_66MHz)
426#define CONFIG_SYS_MAMR_PTA 129
427#else
428#define CONFIG_SYS_MAMR_PTA 98
429#endif
430
431
432
433
434
435
436
437
438
439#define CONFIG_SYS_MPTPR 0x400
440
441
442
443
444
445
446#define CONFIG_SYS_MAMR_8COL 0x68802114
447
448#define CONFIG_SYS_MAMR_9COL 0x68904114
449
450
451
452
453#define CONFIG_SYS_OR0
454#define CONFIG_SYS_BR0
455
456#define CONFIG_SYS_OR1_8COL 0xFF000A00
457#define CONFIG_SYS_BR1_8COL 0x00000081
458#define CONFIG_SYS_OR2_8COL 0xFE000A00
459#define CONFIG_SYS_BR2_8COL 0x01000081
460#define CONFIG_SYS_OR3_8COL 0xFC000A00
461#define CONFIG_SYS_BR3_8COL 0x02000081
462
463#define CONFIG_SYS_OR1_9COL 0xFE000A00
464#define CONFIG_SYS_BR1_9COL 0x00000081
465#define CONFIG_SYS_OR2_9COL 0xFE000A00
466#define CONFIG_SYS_BR2_9COL 0x02000081
467#define CONFIG_SYS_OR3_9COL 0xFE000A00
468#define CONFIG_SYS_BR3_9COL 0x04000081
469
470#define CONFIG_SYS_OR4 0xFFFF8926
471#define CONFIG_SYS_BR4 0x90000401
472
473#define CONFIG_SYS_OR5 0xFFC007F0
474#define CONFIG_SYS_BR5 0x80080801
475
476#define LATCH_ADDR 0x90000200
477
478#define CONFIG_AUTOBOOT_KEYED
479#define CONFIG_AUTOBOOT_STOP_STR "."
480#define CONFIG_SILENT_CONSOLE 1
481#define CONFIG_SYS_DEVICE_NULLDEV 1
482#define CONFIG_VERSION_VARIABLE 1
483
484
485#define CONFIG_OF_LIBFDT 1
486#define CONFIG_OF_BOARD_SETUP 1
487
488#endif
489