1/* 2 * (C) Copyright 2001 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * 10 * Configuration settings for the MUSENKI board. 11 * 12 */ 13 14/* ------------------------------------------------------------------------- */ 15 16/* 17 * board/config.h - configuration options, board specific 18 */ 19 20#ifndef __CONFIG_H 21#define __CONFIG_H 22 23/* 24 * High Level Configuration Options 25 * (easy to change) 26 */ 27 28#define CONFIG_MPC8245 1 29#define CONFIG_MUSENKI 1 30 31#define CONFIG_SYS_TEXT_BASE 0xFFF00000 32 33#define CONFIG_CONS_INDEX 1 34#define CONFIG_BAUDRATE 9600 35 36#define CONFIG_BOOTDELAY 5 37 38 39/* 40 * BOOTP options 41 */ 42#define CONFIG_BOOTP_BOOTFILESIZE 43#define CONFIG_BOOTP_BOOTPATH 44#define CONFIG_BOOTP_GATEWAY 45#define CONFIG_BOOTP_HOSTNAME 46 47 48/* 49 * Command line configuration. 50 */ 51#include <config_cmd_default.h> 52 53 54/* 55 * Miscellaneous configurable options 56 */ 57#undef CONFIG_SYS_LONGHELP /* undef to save memory */ 58#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 59 60/* Print Buffer Size 61 */ 62#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) 63#define CONFIG_SYS_MAXARGS 8 /* Max number of command args */ 64#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 65#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */ 66 67/*----------------------------------------------------------------------- 68 * PCI stuff 69 *----------------------------------------------------------------------- 70 */ 71#define CONFIG_PCI /* include pci support */ 72#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ 73#undef CONFIG_PCI_PNP 74 75 76#define CONFIG_TULIP 77 78#define PCI_ENET0_IOADDR 0x80000000 79#define PCI_ENET0_MEMADDR 0x80000000 80#define PCI_ENET1_IOADDR 0x81000000 81#define PCI_ENET1_MEMADDR 0x81000000 82 83 84/*----------------------------------------------------------------------- 85 * Start addresses for the final memory configuration 86 * (Set up by the startup code) 87 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 88 */ 89#define CONFIG_SYS_SDRAM_BASE 0x00000000 90 91#define CONFIG_SYS_FLASH_BASE0_PRELIM 0xFF800000 /* FLASH bank on RCS#0 */ 92#define CONFIG_SYS_FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank on RCS#1 */ 93#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH_BASE0_PRELIM 94 95/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the 96 * reset vector is actually located at FFB00100, but the 8245 97 * takes care of us. 98 */ 99#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 100 101#define CONFIG_SYS_EUMB_ADDR 0xFC000000 102 103#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 104#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 105#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 106 107#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */ 108#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */ 109 110 /* Maximum amount of RAM. 111 */ 112#define CONFIG_SYS_MAX_RAM_SIZE 0x08000000 /* 0 .. 128 MB of (S)DRAM */ 113 114 115#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE 116#undef CONFIG_SYS_RAMBOOT 117#else 118#define CONFIG_SYS_RAMBOOT 119#endif 120 121/* 122 * NS16550 Configuration 123 */ 124#define CONFIG_SYS_NS16550 125#define CONFIG_SYS_NS16550_SERIAL 126 127#define CONFIG_SYS_NS16550_REG_SIZE 1 128 129#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) 130 131#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500) 132#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600) 133 134/*----------------------------------------------------------------------- 135 * Definitions for initial stack pointer and data area 136 */ 137 138/* #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE */ 139#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 140#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 141#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 142 143 144/* 145 * Low Level Configuration Settings 146 * (address mappings, register initial values, etc.) 147 * You should know what you are doing if you make changes here. 148 * For the detail description refer to the MPC8240 user's manual. 149 */ 150 151#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */ 152 153 /* Bit-field values for MCCR1. 154 */ 155#define CONFIG_SYS_ROMNAL 7 156#define CONFIG_SYS_ROMFAL 11 157#define CONFIG_SYS_DBUS_SIZE 0x3 158 159 /* Bit-field values for MCCR2. 160 */ 161#define CONFIG_SYS_TSWAIT 0x5 /* Transaction Start Wait States timer */ 162#define CONFIG_SYS_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */ 163 164 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. 165 */ 166#define CONFIG_SYS_BSTOPRE 121 167 168 /* Bit-field values for MCCR3. 169 */ 170#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */ 171 172 /* Bit-field values for MCCR4. 173 */ 174#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval FIXME: was 2 */ 175#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */ 176#define CONFIG_SYS_ACTORW 3 /* FIXME was 2 */ 177#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */ 178#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */ 179#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1 180#define CONFIG_SYS_EXTROM 1 181#define CONFIG_SYS_REGDIMM 0 182 183#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/ 184 185#define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */ 186 187/* Memory bank settings. 188 * Only bits 20-29 are actually used from these vales to set the 189 * start/end addresses. The upper two bits will always be 0, and the lower 190 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end 191 * address. Refer to the MPC8240 book. 192 */ 193 194#define CONFIG_SYS_BANK0_START 0x00000000 195#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1) 196#define CONFIG_SYS_BANK0_ENABLE 1 197#define CONFIG_SYS_BANK1_START 0x3ff00000 198#define CONFIG_SYS_BANK1_END 0x3fffffff 199#define CONFIG_SYS_BANK1_ENABLE 0 200#define CONFIG_SYS_BANK2_START 0x3ff00000 201#define CONFIG_SYS_BANK2_END 0x3fffffff 202#define CONFIG_SYS_BANK2_ENABLE 0 203#define CONFIG_SYS_BANK3_START 0x3ff00000 204#define CONFIG_SYS_BANK3_END 0x3fffffff 205#define CONFIG_SYS_BANK3_ENABLE 0 206#define CONFIG_SYS_BANK4_START 0x3ff00000 207#define CONFIG_SYS_BANK4_END 0x3fffffff 208#define CONFIG_SYS_BANK4_ENABLE 0 209#define CONFIG_SYS_BANK5_START 0x3ff00000 210#define CONFIG_SYS_BANK5_END 0x3fffffff 211#define CONFIG_SYS_BANK5_ENABLE 0 212#define CONFIG_SYS_BANK6_START 0x3ff00000 213#define CONFIG_SYS_BANK6_END 0x3fffffff 214#define CONFIG_SYS_BANK6_ENABLE 0 215#define CONFIG_SYS_BANK7_START 0x3ff00000 216#define CONFIG_SYS_BANK7_END 0x3fffffff 217#define CONFIG_SYS_BANK7_ENABLE 0 218 219#define CONFIG_SYS_ODCR 0xff 220 221#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) 222#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 223 224#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE) 225#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP) 226 227#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) 228#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) 229 230#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT) 231#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) 232 233#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L 234#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 235#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 236#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 237#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L 238#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U 239#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L 240#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 241 242/* 243 * For booting Linux, the board info and command line data 244 * have to be in the first 8 MB of memory, since this is 245 * the maximum mapped by the Linux kernel during initialization. 246 */ 247#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 248 249/*----------------------------------------------------------------------- 250 * FLASH organization 251 */ 252#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* Max number of flash banks */ 253#define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors per flash */ 254 255#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 256#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 257 258 259 /* Warining: environment is not EMBEDDED in the U-Boot code. 260 * It's stored in flash separately. 261 */ 262#define CONFIG_ENV_IS_IN_FLASH 1 263#define CONFIG_ENV_ADDR 0xFFFF0000 264#define CONFIG_ENV_SIZE 0x00010000 /* Size of the Environment */ 265#define CONFIG_ENV_SECT_SIZE 0x20000 /* Size of the Environment Sector */ 266 267/*----------------------------------------------------------------------- 268 * Cache Configuration 269 */ 270#define CONFIG_SYS_CACHELINE_SIZE 32 271#if defined(CONFIG_CMD_KGDB) 272# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 273#endif 274 275#endif /* __CONFIG_H */ 276