1/* 2 * (C) Copyright 2000-2008 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * board/config.h - configuration options, board specific 10 */ 11 12#ifndef __CONFIG_H 13#define __CONFIG_H 14 15#undef TQM8xxL_80MHz /* 1 / * define for 80 MHz CPU only */ 16 17/* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21 22#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ 23#define CONFIG_SM850 1 /*...on a MPC850 Service Module */ 24 25#define CONFIG_SYS_TEXT_BASE 0x40000000 26 27#define CONFIG_8xx_CONS_SMC2 1 /* Console is on SMC2 */ 28#define CONFIG_SYS_SMC_RXBUFLEN 128 29#define CONFIG_SYS_MAXIDLE 10 30#define CONFIG_BAUDRATE 115200 31#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 32 33#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ 34 35#define CONFIG_BOARD_TYPES 1 /* support board types */ 36 37#undef CONFIG_BOOTARGS 38#define CONFIG_BOOTCOMMAND \ 39 "bootp; " \ 40 "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ 41 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ 42 "bootm" 43 44#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 45#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 46 47#undef CONFIG_WATCHDOG /* watchdog disabled */ 48 49#undef CONFIG_STATUS_LED /* Status LED not enabled */ 50 51#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 52 53/* 54 * BOOTP options 55 */ 56#define CONFIG_BOOTP_SUBNETMASK 57#define CONFIG_BOOTP_GATEWAY 58#define CONFIG_BOOTP_HOSTNAME 59#define CONFIG_BOOTP_BOOTPATH 60#define CONFIG_BOOTP_BOOTFILESIZE 61 62 63#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 64 65 66/* 67 * Command line configuration. 68 */ 69#include <config_cmd_default.h> 70 71#define CONFIG_CMD_DHCP 72#define CONFIG_CMD_DATE 73 74 75/* 76 * Miscellaneous configurable options 77 */ 78#define CONFIG_SYS_LONGHELP /* undef to save memory */ 79#if defined(CONFIG_CMD_KGDB) && defined(KGDB_DEBUG) 80#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 81#else 82#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 83#endif 84#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 85#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 86#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 87 88#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 89#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 90 91#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 92 93/* 94 * Low Level Configuration Settings 95 * (address mappings, register initial values, etc.) 96 * You should know what you are doing if you make changes here. 97 */ 98/*----------------------------------------------------------------------- 99 * Internal Memory Mapped Register 100 */ 101#define CONFIG_SYS_IMMR 0xFFF00000 102 103/*----------------------------------------------------------------------- 104 * Definitions for initial stack pointer and data area (in DPRAM) 105 */ 106#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 107#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 108#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 109#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 110 111/*----------------------------------------------------------------------- 112 * Start addresses for the final memory configuration 113 * (Set up by the startup code) 114 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 115 */ 116#define CONFIG_SYS_SDRAM_BASE 0x00000000 117#define CONFIG_SYS_FLASH_BASE 0x40000000 118#if defined(DEBUG) 119#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 120#else 121#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ 122#endif 123#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 124#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 125 126/* 127 * For booting Linux, the board info and command line data 128 * have to be in the first 8 MB of memory, since this is 129 * the maximum mapped by the Linux kernel during initialization. 130 */ 131#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 132 133/*----------------------------------------------------------------------- 134 * FLASH organization 135 */ 136/* use CFI flash driver */ 137#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 138#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 139#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } 140#define CONFIG_SYS_FLASH_EMPTY_INFO 141#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 142#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 143#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ 144 145#define CONFIG_ENV_IS_IN_FLASH 1 146#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ 147#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ 148 149#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 150 151/*----------------------------------------------------------------------- 152 * Hardware Information Block 153 */ 154#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 155#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 156#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 157 158/*----------------------------------------------------------------------- 159 * Cache Configuration 160 */ 161#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 162#if defined(CONFIG_CMD_KGDB) 163#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 164#endif 165 166/*----------------------------------------------------------------------- 167 * SYPCR - System Protection Control 11-9 168 * SYPCR can only be written once after reset! 169 *----------------------------------------------------------------------- 170 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 171 */ 172#if defined(CONFIG_WATCHDOG) 173#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 174 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 175#else 176#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 177#endif 178 179/*----------------------------------------------------------------------- 180 * SIUMCR - SIU Module Configuration 11-6 181 *----------------------------------------------------------------------- 182 * PCMCIA config., multi-function pin tri-state 183 */ 184#ifndef CONFIG_CAN_DRIVER 185#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 186#else /* we must activate GPL5 in the SIUMCR for CAN */ 187#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 188#endif /* CONFIG_CAN_DRIVER */ 189 190/*----------------------------------------------------------------------- 191 * TBSCR - Time Base Status and Control 11-26 192 *----------------------------------------------------------------------- 193 * Clear Reference Interrupt Status, Timebase freezing enabled 194 */ 195#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 196 197/*----------------------------------------------------------------------- 198 * RTCSC - Real-Time Clock Status and Control Register 11-27 199 *----------------------------------------------------------------------- 200 */ 201#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 202 203/*----------------------------------------------------------------------- 204 * PISCR - Periodic Interrupt Status and Control 11-31 205 *----------------------------------------------------------------------- 206 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 207 */ 208#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 209 210/*----------------------------------------------------------------------- 211 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 212 *----------------------------------------------------------------------- 213 * Reset PLL lock status sticky bit, timer expired status bit and timer 214 * interrupt status bit 215 * 216 * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! 217 */ 218#ifdef TQM8xxL_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ 219#define CONFIG_SYS_PLPRCR \ 220 ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST ) 221#else 222#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 223#endif /* TQM8xxL_80MHz */ 224 225/*----------------------------------------------------------------------- 226 * SCCR - System Clock and reset Control Register 15-27 227 *----------------------------------------------------------------------- 228 * Set clock output, timebase and RTC source and divider, 229 * power management and some other internal clocks 230 */ 231#define SCCR_MASK SCCR_EBDF11 232#ifdef TQM8xxL_80MHz /* for 80 MHz, we use a 16 MHz clock * 5 */ 233#define CONFIG_SYS_SCCR (/* SCCR_TBS | */ \ 234 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 235 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 236 SCCR_DFALCD00) 237#else /* up to 50 MHz we use a 1:1 clock */ 238#define CONFIG_SYS_SCCR (SCCR_TBS | \ 239 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 240 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 241 SCCR_DFALCD00) 242#endif /* TQM8xxL_80MHz */ 243 244/*----------------------------------------------------------------------- 245 * PCMCIA stuff 246 *----------------------------------------------------------------------- 247 * 248 */ 249#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 250#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 251#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 252#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 253#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 254#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 255#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 256#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 257 258/*----------------------------------------------------------------------- 259 * 260 *----------------------------------------------------------------------- 261 * 262 */ 263#define CONFIG_SYS_DER 0 264 265/* 266 * Init Memory Controller: 267 * 268 * BR0/1 and OR0/1 (FLASH) 269 */ 270 271#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 272#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 273 274/* used to re-map FLASH both when starting from SRAM or FLASH: 275 * restrict access enough to keep SRAM working (if any) 276 * but not too much to meddle with FLASH accesses 277 */ 278#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 279#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 280 281/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ 282#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | \ 283 OR_SCY_5_CLK | OR_EHTR) 284 285#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 286#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 287#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 288 289#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 290#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 291#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 292 293/* 294 * BR2/3 and OR2/3 (SDRAM) 295 * 296 */ 297#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 298#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 299#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 300 301/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 302#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 303 304#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 305#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 306 307#ifndef CONFIG_CAN_DRIVER 308#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 309#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 310#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 311#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 312#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 313#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 314#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 315 BR_PS_8 | BR_MS_UPMB | BR_V ) 316#endif /* CONFIG_CAN_DRIVER */ 317 318/* 319 * Memory Periodic Timer Prescaler 320 */ 321 322/* periodic timer for refresh */ 323#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */ 324 325/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */ 326#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 327#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 328 329/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 330#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 331#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 332 333/* 334 * MAMR settings for SDRAM 335 */ 336 337/* 8 column SDRAM */ 338#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 339 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 340 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 341/* 9 column SDRAM */ 342#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 343 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 344 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 345 346/* pass open firmware flat tree */ 347#define CONFIG_OF_LIBFDT 1 348#define CONFIG_OF_BOARD_SETUP 1 349#define CONFIG_HWCONFIG 1 350 351#endif /* __CONFIG_H */ 352