LXR uboot/include/configs/lwmon.h

   1/*
   2 * (C) Copyright 2001-2005
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8/*
   9 * board/config.h - configuration options, board specific
  10 */
  11
  12#ifndef __CONFIG_H
  13#define __CONFIG_H
  14
  15/* External logbuffer support */
  16#define CONFIG_LOGBUFFER
  17
  18/*
  19 * High Level Configuration Options
  20 * (easy to change)
  21 */
  22
  23#define CONFIG_MPC823           1       /* This is a MPC823E CPU        */
  24#define CONFIG_LWMON            1       /* ...on a LWMON board          */
  25
  26#define CONFIG_SYS_TEXT_BASE    0x40000000
  27
  28/* Default Ethernet MAC address */
  29#define CONFIG_ETHADDR          00:11:B0:00:00:00
  30
  31/* The default Ethernet MAC address can be overwritten just once */
  32#ifdef CONFIG_ETHADDR
  33#define CONFIG_OVERWRITE_ETHADDR_ONCE   1
  34#endif
  35
  36#define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f()    */
  37#define CONFIG_BOARD_POSTCLK_INIT 1     /* Call board_postclk_init()    */
  38#define CONFIG_MISC_INIT_R      1       /* Call misc_init_r()           */
  39
  40#define CONFIG_LCD              1       /* use LCD controller ...       */
  41#define CONFIG_MPC8XX_LCD
  42#define CONFIG_HLD1045          1       /* ... with a HLD1045 display   */
  43
  44#define CONFIG_LCD_LOGO         1       /* print our logo on the LCD    */
  45#define CONFIG_LCD_INFO         1       /* ... and some board info      */
  46#define CONFIG_SPLASH_SCREEN            /* ... with splashscreen support*/
  47
  48#define CONFIG_8xx_CONS_SMC2    1       /* Console is on SMC2           */
  49#define CONFIG_8xx_CONS_SCC2    1       /* Console is on SCC2           */
  50
  51#define CONFIG_BAUDRATE         115200  /* with watchdog >= 38400 needed */
  52
  53#define CONFIG_BOOTDELAY        1       /* autoboot after 1 second      */
  54
  55#define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  56
  57/* pre-boot commands */
  58#define CONFIG_PREBOOT          "setenv bootdelay 15"
  59
  60#undef  CONFIG_BOOTARGS
  61
  62/* POST support */
  63#define CONFIG_POST             (CONFIG_SYS_POST_CACHE     | \
  64                                 CONFIG_SYS_POST_WATCHDOG | \
  65                                 CONFIG_SYS_POST_RTC       | \
  66                                 CONFIG_SYS_POST_MEMORY   | \
  67                                 CONFIG_SYS_POST_CPU       | \
  68                                 CONFIG_SYS_POST_UART      | \
  69                                 CONFIG_SYS_POST_ETHER    | \
  70                                 CONFIG_SYS_POST_I2C       | \
  71                                 CONFIG_SYS_POST_SPI       | \
  72                                 CONFIG_SYS_POST_USB       | \
  73                                 CONFIG_SYS_POST_SPR       | \
  74                                 CONFIG_SYS_POST_SYSMON)
  75
  76/*
  77 * Keyboard commands:
  78 * # = 0x28 = ENTER :           enable bootmessages on LCD
  79 * 2 = 0x3A+0x3C = F1 + F3 :    enable update mode
  80 * 3 = 0x3C+0x3F = F3 + F6 :    enable test mode
  81 */
  82
  83#define CONFIG_BOOTCOMMAND "source 40040000;saveenv"
  84
  85/*      "gatewayip=10.8.211.250\0"                                      \ */
  86#define CONFIG_EXTRA_ENV_SETTINGS                                       \
  87        "kernel_addr=40080000\0"                                        \
  88        "ramdisk_addr=40280000\0"                                       \
  89        "netmask=255.255.192.0\0"                                       \
  90        "serverip=10.8.2.101\0"                                         \
  91        "ipaddr=10.8.57.0\0"                                            \
  92        "magic_keys=#23\0"                                              \
  93        "key_magic#=28\0"                                               \
  94        "key_cmd#=setenv addfb setenv 'bootargs $bootargs console=tty0'\0" \
  95        "key_magic2=3A+3C\0"                                            \
  96        "key_cmd2=echo *** Entering Update Mode ***;"                   \
  97                "if fatload ide 0:3 10000 update.scr;"                  \
  98                        "then source 10000;"                            \
  99                        "else echo *** UPDATE FAILED ***;"              \
 100                "fi\0"                                                  \
 101        "key_magic3=3C+3F\0"                                            \
 102        "key_cmd3=echo *** Entering Test Mode ***;"                     \
 103                "setenv add_misc 'setenv bootargs $bootargs testmode'\0" \
 104        "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath\0" \
 105        "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 106        "addfb=setenv bootargs $bootargs console=ttyS1,$baudrate\0"     \
 107        "addip=setenv bootargs $bootargs "                              \
 108                "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname::off " \
 109                "panic=1\0"                                             \
 110        "add_wdt=setenv bootargs $bootargs $wdt_args\0"                 \
 111        "add_misc=setenv bootargs $bootargs runmode\0"                  \
 112        "flash_nfs=run nfsargs addip add_wdt addfb add_misc;"           \
 113                "bootm $kernel_addr\0"                                  \
 114        "flash_self=run ramargs addip add_wdt addfb add_misc;"          \
 115                "bootm $kernel_addr $ramdisk_addr\0"                    \
 116        "net_nfs=tftp 100000 /tftpboot/uImage.lwmon;"                   \
 117                "run nfsargs addip add_wdt addfb;bootm\0"               \
 118        "rootpath=/opt/eldk/ppc_8xx\0"                                  \
 119        "load=tftp 100000 /tftpboot/u-boot.bin\0"                       \
 120        "update=protect off 1:0;era 1:0;cp.b 100000 40000000 $filesize\0" \
 121        "wdt_args=wdt_8xx=off\0"                                        \
 122        "verify=no"
 123
 124#define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 125#undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
 126
 127#define CONFIG_WATCHDOG         1       /* watchdog enabled             */
 128#define CONFIG_SYS_WATCHDOG_FREQ       (CONFIG_SYS_HZ / 20)
 129
 130#undef  CONFIG_STATUS_LED               /* Status LED disabled          */
 131
 132/* enable I2C and select the hardware/software driver */
 133#define CONFIG_SYS_I2C
 134#define CONFIG_SYS_I2C_SOFT             /* I2C bit-banged */
 135#define CONFIG_SYS_I2C_SOFT_SPEED       93000   /* 93 kHz is supposed to work */
 136#define CONFIG_SYS_I2C_SOFT_SLAVE       0xFE
 137/*
 138 * Software (bit-bang) I2C driver configuration
 139 */
 140#define PB_SCL          0x00000020      /* PB 26 */
 141#define PB_SDA          0x00000010      /* PB 27 */
 142
 143#define I2C_INIT        (immr->im_cpm.cp_pbdir |=  PB_SCL)
 144#define I2C_ACTIVE      (immr->im_cpm.cp_pbdir |=  PB_SDA)
 145#define I2C_TRISTATE    (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 146#define I2C_READ        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 147#define I2C_SDA(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 148                        else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 149#define I2C_SCL(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 150                        else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 151#define I2C_DELAY       udelay(2)       /* 1/4 I2C clock duration */
 152
 153
 154#define CONFIG_RTC_PCF8563              /* use Philips PCF8563 RTC      */
 155
 156
 157/*
 158 * Command line configuration.
 159 */
 160#include <config_cmd_default.h>
 161
 162#define CONFIG_CMD_ASKENV
 163#define CONFIG_CMD_BMP
 164#define CONFIG_CMD_BSP
 165#define CONFIG_CMD_DATE
 166#define CONFIG_CMD_DHCP
 167#define CONFIG_CMD_EEPROM
 168#define CONFIG_CMD_FAT
 169#define CONFIG_CMD_I2C
 170#define CONFIG_CMD_IDE
 171#define CONFIG_CMD_NFS
 172#define CONFIG_CMD_SNTP
 173
 174#ifdef CONFIG_POST
 175#define CONFIG_CMD_DIAG
 176#endif
 177
 178
 179#define CONFIG_MAC_PARTITION
 180#define CONFIG_DOS_PARTITION
 181
 182/*
 183 * BOOTP options
 184 */
 185#define CONFIG_BOOTP_SUBNETMASK
 186#define CONFIG_BOOTP_GATEWAY
 187#define CONFIG_BOOTP_HOSTNAME
 188#define CONFIG_BOOTP_BOOTPATH
 189#define CONFIG_BOOTP_BOOTFILESIZE
 190
 191
 192/*
 193 * Miscellaneous configurable options
 194 */
 195#define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 196
 197#define CONFIG_SYS_HUSH_PARSER          1       /* use "hush" command parser    */
 198
 199#if defined(CONFIG_CMD_KGDB)
 200#define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 201#else
 202#define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 203#endif
 204#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 205#define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 206#define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 207
 208#define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on     */
 209#define CONFIG_SYS_MEMTEST_END          0x00F00000      /* 1 ... 15MB in DRAM   */
 210
 211#define CONFIG_SYS_LOAD_ADDR            0x00100000      /* default load address */
 212
 213#define CONFIG_SYS_PIO_MODE             0       /* IDE interface in PIO Mode 0  */
 214
 215/*
 216 * When the watchdog is enabled, output must be fast enough in Linux.
 217 */
 218#ifdef CONFIG_WATCHDOG
 219#define CONFIG_SYS_BAUDRATE_TABLE       {               38400, 57600, 115200 }
 220#endif
 221
 222/*----------------------------------------------------------------------*/
 223#define CONFIG_MODEM_SUPPORT    1       /* enable modem initialization stuff */
 224#undef CONFIG_MODEM_SUPPORT_DEBUG
 225
 226#define CONFIG_MODEM_KEY_MAGIC  "3C+3D" /* press F3 + F4 keys to enable modem */
 227#define CONFIG_POST_KEY_MAGIC   "3C+3E" /* press F3 + F5 keys to force POST */
 228#if 0
 229#define CONFIG_AUTOBOOT_KEYED           /* Enable "password" protection */
 230#define CONFIG_AUTOBOOT_PROMPT  \
 231        "\nEnter password - autoboot in %d sec...\n", bootdelay
 232#define CONFIG_AUTOBOOT_DELAY_STR       "  "    /* "password"   */
 233#endif
 234/*----------------------------------------------------------------------*/
 235
 236/*
 237 * Low Level Configuration Settings
 238 * (address mappings, register initial values, etc.)
 239 * You should know what you are doing if you make changes here.
 240 */
 241/*-----------------------------------------------------------------------
 242 * Internal Memory Mapped Register
 243 */
 244#define CONFIG_SYS_IMMR         0xFFF00000
 245
 246/*-----------------------------------------------------------------------
 247 * Definitions for initial stack pointer and data area (in DPRAM)
 248 */
 249#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 250#define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 251#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 252#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 253
 254/*-----------------------------------------------------------------------
 255 * Start addresses for the final memory configuration
 256 * (Set up by the startup code)
 257 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 258 */
 259#define CONFIG_SYS_SDRAM_BASE           0x00000000
 260#define CONFIG_SYS_FLASH_BASE           0x40000000
 261#if defined(DEBUG) || defined(CONFIG_CMD_IDE)
 262#define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 263#else
 264#define CONFIG_SYS_MONITOR_LEN          (128 << 10)     /* Reserve 128 kB for Monitor   */
 265#endif
 266#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 267#define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 268
 269/*
 270 * For booting Linux, the board info and command line data
 271 * have to be in the first 8 MB of memory, since this is
 272 * the maximum mapped by the Linux kernel during initialization.
 273 */
 274#define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 275/*-----------------------------------------------------------------------
 276 * FLASH organization
 277 */
 278#define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks           */
 279#define CONFIG_SYS_MAX_FLASH_SECT       128     /* max number of sectors on one chip    */
 280
 281#define CONFIG_SYS_FLASH_ERASE_TOUT     180000  /* Timeout for Flash Erase (in ms)      */
 282#define CONFIG_SYS_FLASH_WRITE_TOUT     600     /* Timeout for Flash Write (in ms)      */
 283#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 284#define CONFIG_SYS_FLASH_BUFFER_WRITE_TOUT      2048    /* Timeout for Flash Buffer Write (in ms)       */
 285/* Buffer size.
 286   We have two flash devices connected in parallel.
 287   Each device incorporates a Write Buffer of 32 bytes.
 288 */
 289#define CONFIG_SYS_FLASH_BUFFER_SIZE    (2*32)
 290
 291/* Put environment in flash which is much faster to boot than using the EEPROM  */
 292#define CONFIG_ENV_IS_IN_FLASH  1
 293#define CONFIG_ENV_ADDR     0x40040000  /* Address    of Environment Sector     */
 294#define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment            */
 295#define CONFIG_ENV_SECT_SIZE    0x40000 /* we have BIG sectors only :-(         */
 296
 297/*-----------------------------------------------------------------------
 298 * I2C/EEPROM Configuration
 299 */
 300
 301#define CONFIG_SYS_I2C_AUDIO_ADDR       0x28    /* Audio volume control                 */
 302#define CONFIG_SYS_I2C_SYSMON_ADDR      0x2E    /* LM87 System Monitor                  */
 303#define CONFIG_SYS_I2C_RTC_ADDR 0x51    /* PCF8563 RTC                          */
 304#define CONFIG_SYS_I2C_POWER_A_ADDR     0x52    /* PCMCIA/USB power switch, channel A   */
 305#define CONFIG_SYS_I2C_POWER_B_ADDR     0x53    /* PCMCIA/USB power switch, channel B   */
 306#define CONFIG_SYS_I2C_KEYBD_ADDR       0x56    /* PIC LWE keyboard                     */
 307#define CONFIG_SYS_I2C_PICIO_ADDR       0x57    /* PIC IO Expander                      */
 308
 309#undef  CONFIG_USE_FRAM                 /* Use FRAM instead of EEPROM   */
 310
 311#ifdef CONFIG_USE_FRAM  /* use FRAM */
 312#define CONFIG_SYS_I2C_EEPROM_ADDR      0x55    /* FRAM FM24CL64                */
 313#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 314#else                   /* use EEPROM */
 315#define CONFIG_SYS_I2C_EEPROM_ADDR      0x58    /* EEPROM AT24C164              */
 316#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 317#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* takes up to 10 msec  */
 318#endif  /* CONFIG_USE_FRAM */
 319#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 320
 321/* List of I2C addresses to be verified by POST */
 322#ifdef CONFIG_USE_FRAM
 323#define CONFIG_SYS_POST_I2C_ADDRS       {/* CONFIG_SYS_I2C_AUDIO_ADDR, */ \
 324                                         CONFIG_SYS_I2C_SYSMON_ADDR,    \
 325                                         CONFIG_SYS_I2C_RTC_ADDR,       \
 326                                         CONFIG_SYS_I2C_POWER_A_ADDR,   \
 327                                         CONFIG_SYS_I2C_POWER_B_ADDR,   \
 328                                         CONFIG_SYS_I2C_KEYBD_ADDR,     \
 329                                         CONFIG_SYS_I2C_PICIO_ADDR,     \
 330                                         CONFIG_SYS_I2C_EEPROM_ADDR,    \
 331                                        }
 332#else   /* Use EEPROM - which show up on 8 consequtive addresses */
 333#define CONFIG_SYS_POST_I2C_ADDRS       {/* CONFIG_SYS_I2C_AUDIO_ADDR, */ \
 334                                         CONFIG_SYS_I2C_SYSMON_ADDR,    \
 335                                         CONFIG_SYS_I2C_RTC_ADDR,       \
 336                                         CONFIG_SYS_I2C_POWER_A_ADDR,   \
 337                                         CONFIG_SYS_I2C_POWER_B_ADDR,   \
 338                                         CONFIG_SYS_I2C_KEYBD_ADDR,     \
 339                                         CONFIG_SYS_I2C_PICIO_ADDR,     \
 340                                         CONFIG_SYS_I2C_EEPROM_ADDR+0,  \
 341                                         CONFIG_SYS_I2C_EEPROM_ADDR+1,  \
 342                                         CONFIG_SYS_I2C_EEPROM_ADDR+2,  \
 343                                         CONFIG_SYS_I2C_EEPROM_ADDR+3,  \
 344                                         CONFIG_SYS_I2C_EEPROM_ADDR+4,  \
 345                                         CONFIG_SYS_I2C_EEPROM_ADDR+5,  \
 346                                         CONFIG_SYS_I2C_EEPROM_ADDR+6,  \
 347                                         CONFIG_SYS_I2C_EEPROM_ADDR+7,  \
 348                                        }
 349#endif  /* CONFIG_USE_FRAM */
 350
 351/*-----------------------------------------------------------------------
 352 * Cache Configuration
 353 */
 354#define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 355#if defined(CONFIG_CMD_KGDB)
 356#define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 357#endif
 358
 359/*-----------------------------------------------------------------------
 360 * SYPCR - System Protection Control                            11-9
 361 * SYPCR can only be written once after reset!
 362 *-----------------------------------------------------------------------
 363 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 364 */
 365#if 0 && defined(CONFIG_WATCHDOG)       /* LWMON uses external MAX706TESA WD */
 366#define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 367                         SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 368#else
 369#define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 370#endif
 371
 372/*-----------------------------------------------------------------------
 373 * SIUMCR - SIU Module Configuration                            11-6
 374 *-----------------------------------------------------------------------
 375 * PCMCIA config., multi-function pin tri-state
 376 */
 377/* EARB, DBGC and DBPC are initialised by the HCW */
 378/* => 0x000000C0 */
 379#define CONFIG_SYS_SIUMCR       (SIUMCR_GB5E)
 380/*#define CONFIG_SYS_SIUMCR     (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) */
 381
 382/*-----------------------------------------------------------------------
 383 * TBSCR - Time Base Status and Control                         11-26
 384 *-----------------------------------------------------------------------
 385 * Clear Reference Interrupt Status, Timebase freezing enabled
 386 */
 387#define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 388
 389/*-----------------------------------------------------------------------
 390 * PISCR - Periodic Interrupt Status and Control                11-31
 391 *-----------------------------------------------------------------------
 392 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 393 */
 394#define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 395
 396/*-----------------------------------------------------------------------
 397 * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 398 *-----------------------------------------------------------------------
 399 * Reset PLL lock status sticky bit, timer expired status bit and timer
 400 * interrupt status bit, set PLL multiplication factor !
 401 */
 402/* 0x00405000 */
 403#define CONFIG_SYS_PLPRCR_MF    4       /* (4+1) * 13.2 = 66 MHz Clock */
 404#define CONFIG_SYS_PLPRCR                                                       \
 405                (       (CONFIG_SYS_PLPRCR_MF << PLPRCR_MF_SHIFT) |             \
 406                        PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST |    \
 407                        /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |            \
 408                        PLPRCR_CSR    /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/   \
 409                )
 410
 411#define CONFIG_8xx_GCLK_FREQ    ((CONFIG_SYS_PLPRCR_MF+1)*13200000)
 412
 413/*-----------------------------------------------------------------------
 414 * SCCR - System Clock and reset Control Register               15-27
 415 *-----------------------------------------------------------------------
 416 * Set clock output, timebase and RTC source and divider,
 417 * power management and some other internal clocks
 418 */
 419#define SCCR_MASK       SCCR_EBDF11
 420/* 0x01800000 */
 421#define CONFIG_SYS_SCCR (SCCR_COM00     | /*SCCR_TBS|*/         \
 422                         SCCR_RTDIV     |   SCCR_RTSEL    |     \
 423                         /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/       \
 424                         SCCR_EBDF00 |   SCCR_DFSYNC00 |        \
 425                         SCCR_DFBRG00   |   SCCR_DFNL000  |     \
 426                         SCCR_DFNH000   |   SCCR_DFLCD100 |     \
 427                         SCCR_DFALCD01)
 428
 429/*-----------------------------------------------------------------------
 430 * RTCSC - Real-Time Clock Status and Control Register          11-27
 431 *-----------------------------------------------------------------------
 432 */
 433/* 0x00C3 => 0x0003 */
 434#define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 435
 436
 437/*-----------------------------------------------------------------------
 438 * RCCR - RISC Controller Configuration Register                19-4
 439 *-----------------------------------------------------------------------
 440 */
 441#define CONFIG_SYS_RCCR 0x0000
 442
 443/*-----------------------------------------------------------------------
 444 * RMDS - RISC Microcode Development Support Control Register
 445 *-----------------------------------------------------------------------
 446 */
 447#define CONFIG_SYS_RMDS 0
 448
 449/*-----------------------------------------------------------------------
 450 *
 451 * Interrupt Levels
 452 *-----------------------------------------------------------------------
 453 */
 454#define CONFIG_SYS_CPM_INTERRUPT        13      /* SIU_LEVEL6   */
 455
 456/*-----------------------------------------------------------------------
 457 * PCMCIA stuff
 458 *-----------------------------------------------------------------------
 459 *
 460 */
 461#define CONFIG_SYS_PCMCIA_MEM_ADDR      (0x50000000)
 462#define CONFIG_SYS_PCMCIA_MEM_SIZE      ( 64 << 20 )
 463#define CONFIG_SYS_PCMCIA_DMA_ADDR      (0x54000000)
 464#define CONFIG_SYS_PCMCIA_DMA_SIZE      ( 64 << 20 )
 465#define CONFIG_SYS_PCMCIA_ATTRB_ADDR    (0x58000000)
 466#define CONFIG_SYS_PCMCIA_ATTRB_SIZE    ( 64 << 20 )
 467#define CONFIG_SYS_PCMCIA_IO_ADDR       (0x5C000000)
 468#define CONFIG_SYS_PCMCIA_IO_SIZE       ( 64 << 20 )
 469
 470/*-----------------------------------------------------------------------
 471 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 472 *-----------------------------------------------------------------------
 473 */
 474
 475#define CONFIG_IDE_PREINIT      1       /* Use preinit IDE hook */
 476#define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 477
 478#undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 479#undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 480#undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 481
 482#define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 483#define CONFIG_SYS_IDE_MAXDEVICE        1       /* max. 1 drive per IDE bus     */
 484
 485#define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 486
 487#define CONFIG_SYS_ATA_BASE_ADDR        CONFIG_SYS_PCMCIA_MEM_ADDR
 488
 489/* Offset for data I/O                  */
 490#define CONFIG_SYS_ATA_DATA_OFFSET      (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 491
 492/* Offset for normal register accesses  */
 493#define CONFIG_SYS_ATA_REG_OFFSET       (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320)
 494
 495/* Offset for alternate registers       */
 496#define CONFIG_SYS_ATA_ALT_OFFSET       0x0100
 497
 498#define CONFIG_SUPPORT_VFAT             /* enable VFAT support */
 499
 500/*-----------------------------------------------------------------------
 501 *
 502 *-----------------------------------------------------------------------
 503 *
 504 */
 505#define CONFIG_SYS_DER 0
 506
 507/*
 508 * Init Memory Controller:
 509 *
 510 * BR0/1 and OR0/1 (FLASH) - second Flash bank optional
 511 */
 512
 513#define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 514#define FLASH_BASE1_PRELIM      0x41000000      /* FLASH bank #1        */
 515
 516/* used to re-map FLASH:
 517 * restrict access enough to keep SRAM working (if any)
 518 * but not too much to meddle with FLASH accesses
 519 */
 520#define CONFIG_SYS_REMAP_OR_AM          0xFF000000      /* OR addr mask */
 521#define CONFIG_SYS_PRELIM_OR_AM 0xFF000000      /* OR addr mask */
 522
 523/* FLASH timing: ACS = 00, TRLX = 0, CSNT = 1, SCY = 8, EHTR = 0        */
 524#define CONFIG_SYS_OR_TIMING_FLASH      (OR_SCY_8_CLK)
 525
 526#define CONFIG_SYS_OR0_REMAP    ( CONFIG_SYS_REMAP_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
 527                                CONFIG_SYS_OR_TIMING_FLASH)
 528#define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \
 529                                CONFIG_SYS_OR_TIMING_FLASH)
 530/* 16 bit, bank valid */
 531#define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
 532
 533#define CONFIG_SYS_OR1_REMAP    CONFIG_SYS_OR0_REMAP
 534#define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 535#define CONFIG_SYS_BR1_PRELIM   ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_32 | BR_V )
 536
 537/*
 538 * BR3/OR3: SDRAM
 539 *
 540 * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
 541 */
 542#define SDRAM_BASE3_PRELIM      0x00000000      /* SDRAM bank */
 543#define SDRAM_PRELIM_OR_AM      0xF0000000      /* map 256 MB (>SDRAM_MAX_SIZE!) */
 544#define SDRAM_TIMING            OR_SCY_0_CLK    /* SDRAM-Timing */
 545
 546#define SDRAM_MAX_SIZE          0x08000000      /* max 128 MB SDRAM */
 547
 548#define CONFIG_SYS_OR3_PRELIM   (SDRAM_PRELIM_OR_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING )
 549#define CONFIG_SYS_BR3_PRELIM   ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 550
 551/*
 552 * BR5/OR5: Touch Panel
 553 *
 554 * AM=0xFFC00 ATM=0 CSNT/SAM=0 ACS/G5LA/G5LS=3 BIH=1 SCY=0 SETA=0 TRLX=0 EHTR=0
 555 */
 556#define TOUCHPNL_BASE           0x20000000
 557#define TOUCHPNL_OR_AM          0xFFFF8000
 558#define TOUCHPNL_TIMING         OR_SCY_0_CLK
 559
 560#define CONFIG_SYS_OR5_PRELIM   (TOUCHPNL_OR_AM | OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \
 561                         TOUCHPNL_TIMING )
 562#define CONFIG_SYS_BR5_PRELIM   ((TOUCHPNL_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
 563
 564#define CONFIG_SYS_MEMORY_75
 565#undef  CONFIG_SYS_MEMORY_7E
 566#undef  CONFIG_SYS_MEMORY_8E
 567
 568/*
 569 * Memory Periodic Timer Prescaler
 570 */
 571
 572/* periodic timer for refresh */
 573#define CONFIG_SYS_MPTPR        0x200
 574
 575/*
 576 * MAMR settings for SDRAM
 577 */
 578
 579#define CONFIG_SYS_MAMR_8COL    0x80802114
 580#define CONFIG_SYS_MAMR_9COL    0x80904114
 581
 582/*
 583 * MAR setting for SDRAM
 584 */
 585#define CONFIG_SYS_MAR          0x00000088
 586
 587#endif  /* __CONFIG_H */
 588