1/* 2 * (C) Copyright 2006-2008 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8#ifndef __CONFIG_H 9#define __CONFIG_H 10 11/* 12 * High Level Configuration Options 13 * (easy to change) 14 */ 15 16#define CONFIG_MPC5200 17#define CONFIG_MCC200 1 /* MCC200 board */ 18 19/* 20 * Valid values for CONFIG_SYS_TEXT_BASE are: 21 * 0xFC000000 boot low (standard configuration) 22 * 0xFFF00000 boot high 23 * 0x00100000 boot from RAM (for testing only) 24 */ 25#ifndef CONFIG_SYS_TEXT_BASE 26#define CONFIG_SYS_TEXT_BASE 0xFC000000 27#endif 28 29#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33MHz */ 30 31#define CONFIG_MISC_INIT_R 32 33#define CONFIG_HIGH_BATS 1 /* High BATs supported */ 34 35/* 36 * Serial console configuration 37 * 38 * To select console on the one of 8 external UARTs, 39 * define CONFIG_QUART_CONSOLE as 1, 2, 3, or 4 for the first Quad UART, 40 * or as 5, 6, 7, or 8 for the second Quad UART. 41 * COM11, COM12, COM13, COM14 are located on the second Quad UART. 42 * 43 * CONFIG_PSC_CONSOLE must be undefined in this case. 44 */ 45#if !defined(CONFIG_PRS200) 46/* MCC200 configuration: */ 47#ifdef CONFIG_CONSOLE_COM12 48#define CONFIG_QUART_CONSOLE 6 /* console is on UARTF of QUART2 */ 49#else 50#define CONFIG_QUART_CONSOLE 8 /* console is on UARTH of QUART2 */ 51#endif 52#else 53/* PRS200 configuration: */ 54#undef CONFIG_QUART_CONSOLE 55#endif /* CONFIG_PRS200 */ 56/* 57 * To select console on PSC1, define CONFIG_PSC_CONSOLE as 1 58 * and undefine CONFIG_QUART_CONSOLE. 59 */ 60#if !defined(CONFIG_PRS200) 61/* MCC200 configuration: */ 62#define CONFIG_PSC_CONSOLE 1 /* PSC1 may be COM */ 63#define CONFIG_PSC_CONSOLE2 2 /* PSC2 is PSoC */ 64#else 65/* PRS200 configuration: */ 66#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ 67#endif 68#define CONFIG_BAUDRATE 115200 69#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } 70 71#define CONFIG_MII 1 72 73#define CONFIG_DOS_PARTITION 74 75/* USB */ 76#define CONFIG_USB_OHCI 77#define CONFIG_USB_STORAGE 78/* automatic software updates (see board/mcc200/auto_update.c) */ 79#define CONFIG_AUTO_UPDATE 1 80 81 82/* 83 * BOOTP options 84 */ 85#define CONFIG_BOOTP_BOOTFILESIZE 86#define CONFIG_BOOTP_BOOTPATH 87#define CONFIG_BOOTP_GATEWAY 88#define CONFIG_BOOTP_HOSTNAME 89 90 91/* 92 * Command line configuration. 93 */ 94#include <config_cmd_default.h> 95 96#define CONFIG_CMD_BEDBUG 97#define CONFIG_CMD_FAT 98#define CONFIG_CMD_I2C 99#define CONFIG_CMD_USB 100 101#undef CONFIG_CMD_NET 102#undef CONFIG_CMD_NFS 103 104/* 105 * Autobooting 106 */ 107#define CONFIG_BOOTDELAY 1 /* autoboot after 1 second */ 108 109#define CONFIG_PREBOOT "echo;" \ 110 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 111 "echo" 112 113#undef CONFIG_BOOTARGS 114 115#ifdef CONFIG_PRS200 116# define CONFIG_SYS__BOARDNAME "prs200" 117# define CONFIG_SYS__LINUX_CONSOLE "ttyS0" 118#else 119# define CONFIG_SYS__BOARDNAME "mcc200" 120# define CONFIG_SYS__LINUX_CONSOLE "ttyEU5" 121#endif 122 123/* Network */ 124#define CONFIG_ETHADDR 00:17:17:ff:00:00 125#define CONFIG_IPADDR 10.76.9.29 126#define CONFIG_SERVERIP 10.76.9.1 127 128#include <version.h> /* For U-Boot version */ 129 130#define CONFIG_EXTRA_ENV_SETTINGS \ 131 "ubootver=" U_BOOT_VERSION "\0" \ 132 "netdev=eth0\0" \ 133 "hostname=" CONFIG_SYS__BOARDNAME "\0" \ 134 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 135 "nfsroot=${serverip}:${rootpath}\0" \ 136 "ramargs=setenv bootargs root=/dev/mtdblock2 " \ 137 "rootfstype=cramfs\0" \ 138 "addip=setenv bootargs ${bootargs} " \ 139 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 140 ":${hostname}:${netdev}:off panic=1\0" \ 141 "addcons=setenv bootargs ${bootargs} " \ 142 "console=${console},${baudrate} " \ 143 "ubootver=${ubootver} board=${board}\0" \ 144 "flash_nfs=run nfsargs addip addcons;" \ 145 "bootm ${kernel_addr}\0" \ 146 "flash_self=run ramargs addip addcons;" \ 147 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 148 "net_nfs=tftp 200000 ${bootfile};" \ 149 "run nfsargs addip addcons;bootm\0" \ 150 "console=" CONFIG_SYS__LINUX_CONSOLE "\0" \ 151 "rootpath=/opt/eldk/ppc_6xx\0" \ 152 "bootfile=/tftpboot/" CONFIG_SYS__BOARDNAME "/uImage\0" \ 153 "load=tftp 200000 /tftpboot/" CONFIG_SYS__BOARDNAME "/u-boot.bin\0" \ 154 "text_base=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ 155 "kernel_addr=0xFC0C0000\0" \ 156 "update=protect off ${text_base} +${filesize};" \ 157 "era ${text_base} +${filesize};" \ 158 "cp.b 200000 ${text_base} ${filesize}\0" \ 159 "unlock=yes\0" \ 160 "" 161 162#define CONFIG_BOOTCOMMAND "run flash_self" 163 164#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ 165 166/* 167 * IPB Bus clocking configuration. 168 */ 169#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ 170 171/* 172 * I2C configuration 173 */ 174#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ 175#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ 176 177#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ 178#define CONFIG_SYS_I2C_SLAVE 0x7F 179 180/* 181 * Flash configuration (8,16 or 32 MB) 182 * TEXT base always at 0xFFF00000 183 * ENV_ADDR always at 0xFFF40000 184 * FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!) 185 * 0xFE000000 for 32 MB 186 * 0xFF000000 for 16 MB 187 * 0xFF800000 for 8 MB 188 */ 189#define CONFIG_SYS_FLASH_BASE 0xfc000000 190#define CONFIG_SYS_FLASH_SIZE 0x04000000 191 192#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ 193#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ 194 195#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 196 197#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 198#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ 199 200#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ 201#define CONFIG_SYS_FLASH_PROTECTION 1 /* hardware flash protection */ 202 203#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 204#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 205 206#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 207#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ 208 209#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ 210 211#define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ 212#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 213#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ 214 215/* Address and size of Redundant Environment Sector */ 216#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) 217#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 218 219#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ 220 221#if CONFIG_SYS_TEXT_BASE == CONFIG_SYS_FLASH_BASE 222#define CONFIG_SYS_LOWBOOT 1 223#endif 224 225/* 226 * Memory map 227 */ 228#define CONFIG_SYS_MBAR 0xf0000000 229#define CONFIG_SYS_SDRAM_BASE 0x00000000 230#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 231 232/* Use SRAM until RAM will be available */ 233#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM 234#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ 235 236 237#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 238#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 239 240#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 241#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 242# define CONFIG_SYS_RAMBOOT 1 243#endif 244 245#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 246#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ 247#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 248 249/* 250 * Ethernet configuration 251 */ 252/* #define CONFIG_MPC5xxx_FEC 1 */ 253/* #define CONFIG_MPC5xxx_FEC_MII100 */ 254/* 255 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb 256 */ 257/* #define CONFIG_MPC5xxx_FEC_MII10 */ 258#define CONFIG_PHY_ADDR 1 259 260/* 261 * LCD Splash Screen 262 */ 263#if !defined(CONFIG_PRS200) 264#define CONFIG_LCD 1 265#define CONFIG_PROGRESSBAR 1 266#endif 267 268#if defined(CONFIG_LCD) 269#define CONFIG_SPLASH_SCREEN 1 270#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 271#define LCD_BPP LCD_MONOCHROME 272#endif 273 274/* 275 * GPIO configuration 276 */ 277/* 0x10000004 = 32MB SDRAM */ 278/* 0x90000004 = 64MB SDRAM */ 279#if defined(CONFIG_LCD) 280/* set PSC2 in UART mode */ 281#define CONFIG_SYS_GPS_PORT_CONFIG 0x00000044 282#else 283#define CONFIG_SYS_GPS_PORT_CONFIG 0x00000004 284#endif 285 286/* 287 * Miscellaneous configurable options 288 */ 289#define CONFIG_SYS_LONGHELP /* undef to save memory */ 290#if defined(CONFIG_CMD_KGDB) 291#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 292#else 293#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 294#endif 295#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 296#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 297#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 298 299#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ 300#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ 301 302#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 303 304#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ 305#if defined(CONFIG_CMD_KGDB) 306# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 307#endif 308 309/* 310 * Various low-level settings 311 */ 312#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI 313#define CONFIG_SYS_HID0_FINAL HID0_ICE 314 315#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE 316#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE 317#define CONFIG_SYS_BOOTCS_CFG 0x0004fb00 318#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE 319#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE 320 321/* Quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */ 322#define CONFIG_SYS_CS2_START 0x80000000 323#define CONFIG_SYS_CS2_SIZE 0x00001000 324#define CONFIG_SYS_CS2_CFG 0x1d300 325 326/* Second Quad UART @0x80010000 */ 327#define CONFIG_SYS_CS1_START 0x80010000 328#define CONFIG_SYS_CS1_SIZE 0x00001000 329#define CONFIG_SYS_CS1_CFG 0x1d300 330 331/* Leica - build revision resistors */ 332/* 333#define CONFIG_SYS_CS3_START 0x80020000 334#define CONFIG_SYS_CS3_SIZE 0x00000004 335#define CONFIG_SYS_CS3_CFG 0x1d300 336*/ 337 338/* 339 * Select one of quarts as a default 340 * console. If undefined - PSC console 341 * wil be default 342 */ 343#define CONFIG_SYS_CS_BURST 0x00000000 344#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 345 346#define CONFIG_SYS_RESET_ADDRESS 0xff000000 347 348/* 349 * QUART Expanders support 350 */ 351#if defined(CONFIG_QUART_CONSOLE) 352/* 353 * We'll use NS16550 chip routines, 354 */ 355#define CONFIG_SYS_NS16550 1 356#define CONFIG_SYS_NS16550_SERIAL 1 357#define CONFIG_CONS_INDEX 1 358/* 359 * To achieve necessary offset on SC16C554 360 * A0-A2 (register select) pins with NS16550 361 * functions (in struct NS16550), REG_SIZE 362 * should be 4, because A0-A2 pins are connected 363 * to DA2-DA4 address bus lines. 364 */ 365#define CONFIG_SYS_NS16550_REG_SIZE 4 366/* 367 * LocalPlus Bus already inited in cpu_init_f(), 368 * so can work with QUART's chip selects. 369 * One of four SC16C554 UARTs is selected with 370 * A3-A4 (DA5-DA6) lines. 371 */ 372#if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5) && !defined(CONFIG_PRS200) 373#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5) 374#elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9) 375#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5) 376#else 377#error "Wrong QUART expander number." 378#endif 379 380/* 381 * SC16C554 chip's external crystal oscillator frequency 382 * is 7.3728 MHz 383 */ 384#define CONFIG_SYS_NS16550_CLK 7372800 385#endif /* CONFIG_QUART_CONSOLE */ 386/*----------------------------------------------------------------------- 387 * USB stuff 388 *----------------------------------------------------------------------- 389 */ 390#define CONFIG_USB_CLOCK 0x0001BBBB 391#define CONFIG_USB_CONFIG 0x00005000 392 393#define CONFIG_AUTOBOOT_KEYED /* use key strings to stop autoboot */ 394#define CONFIG_AUTOBOOT_STOP_STR "432" 395#define CONFIG_SILENT_CONSOLE 1 396 397#endif /* __CONFIG_H */ 398