1/* 2 * (C) Copyright 2006 3 * Stefan Roese, DENX Software Engineering, sr@denx.de. 4 * 5 * Based on original work by 6 * Roel Loeffen, (C) Copyright 2006 Prodrive B.V. 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11/************************************************************************ 12 * p3mx.h - configuration for Prodrive P3M750 & P3M7448 boards 13 * 14 * The defines: 15 * CONFIG_P3M750 or 16 * CONFIG_P3M7448 17 * are written into include/config.h by the "make xxx_config" command 18 ***********************************************************************/ 19#ifndef __CONFIG_H 20#define __CONFIG_H 21 22/*----------------------------------------------------------------------- 23 * High Level Configuration Options 24 *----------------------------------------------------------------------*/ 25#define CONFIG_P3Mx /* used for both board versions */ 26 27#define CONFIG_SYS_TEXT_BASE 0xfff00000 28 29#if defined (CONFIG_P3M750) 30#define CONFIG_750FX /* 750GL/GX/FX */ 31#define CONFIG_HIGH_BATS /* High BATs supported */ 32#define CONFIG_SYS_BOARD_NAME "P3M750" 33#define CONFIG_SYS_BUS_CLK 100000000 34#define CONFIG_SYS_TCLK 100000000 35#elif defined (CONFIG_P3M7448) 36#define CONFIG_74xx 37#define CONFIG_SYS_BOARD_NAME "P3M7448" 38#define CONFIG_SYS_BUS_CLK 133333333 39#define CONFIG_SYS_TCLK 133333333 40#endif 41#define CONFIG_SYS_GT_DUAL_CPU /* also for JTAG even with one cpu */ 42 43/* which initialization functions to call for this board */ 44#define CONFIG_SYS_BOARD_ASM_INIT 1 45#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ 46#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */ 47 48/*----------------------------------------------------------------------- 49 * Base addresses -- Note these are effective addresses where the 50 * actual resources get mapped (not physical addresses) 51 *----------------------------------------------------------------------*/ 52#define CONFIG_SYS_SDRAM_BASE 0x00000000 53#ifdef CONFIG_P3M750 54#define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* each 256 MByte */ 55#endif 56 57#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 58#if defined (CONFIG_P3M750) 59#define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of flash banks */ 60#define CONFIG_SYS_BOOT_SIZE _8M /* boot flash */ 61#elif defined (CONFIG_P3M7448) 62#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of flash banks */ 63#define CONFIG_SYS_BOOT_SIZE _16M /* boot flash */ 64#endif 65#define CONFIG_SYS_BOOT_SPACE CONFIG_SYS_FLASH_BASE /* BOOT_CS0 flash 0 */ 66#define CONFIG_SYS_MONITOR_BASE 0xfff00000 67#define CONFIG_SYS_RESET_ADDRESS 0xfff00100 68#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */ 69#define CONFIG_SYS_MISC_REGION_BASE 0xf0000000 70 71#define CONFIG_SYS_DFL_GT_REGS 0xf1000000 /* boot time GT_REGS */ 72#define CONFIG_SYS_GT_REGS 0xf1000000 /* GT Registers are mapped here */ 73#define CONFIG_SYS_INT_SRAM_BASE 0x42000000 /* GT offers 256k internal SRAM */ 74 75/*----------------------------------------------------------------------- 76 * Initial RAM & stack pointer (placed in internal SRAM) 77 *----------------------------------------------------------------------*/ 78 /* 79 * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS 80 * To an unused memory region. The stack will remain in cache until RAM 81 * is initialized 82*/ 83#undef CONFIG_SYS_INIT_RAM_LOCK 84#define CONFIG_SYS_INIT_RAM_ADDR 0x42000000 85#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 86#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 87 88 89/*----------------------------------------------------------------------- 90 * Serial Port 91 *----------------------------------------------------------------------*/ 92#define CONFIG_MPSC /* MV64460 Serial */ 93#define CONFIG_MPSC_PORT 0 94#define CONFIG_BAUDRATE 115200 /* console baudrate */ 95#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } 96#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 97#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ 98 99/*----------------------------------------------------------------------- 100 * Ethernet 101 *----------------------------------------------------------------------*/ 102/* Change the default ethernet port, use this define (options: 0, 1, 2) */ 103#define CONFIG_SYS_ETH_PORT ETH_0 104#define MV_ETH_DEVS 2 105#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ 106#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ 107 108/*----------------------------------------------------------------------- 109 * FLASH related 110 *----------------------------------------------------------------------*/ 111#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ 112#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ 113#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 114#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ 115#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ 116#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ 117#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ 118#define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */ 119#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ 120 121#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ 122#if defined (CONFIG_P3M750) 123#define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (1 device) */ 124#elif defined (CONFIG_P3M7448) 125#define CONFIG_ENV_SECT_SIZE 0x40000 /* two sectors (2 devices parallel */ 126#endif 127#define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ 128#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) 129 130/*----------------------------------------------------------------------- 131 * DDR SDRAM 132 *----------------------------------------------------------------------*/ 133#define CONFIG_MV64460_ECC 134 135/*----------------------------------------------------------------------- 136 * I2C 137 *----------------------------------------------------------------------*/ 138#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed default */ 139 140/* I2C RTC */ 141#define CONFIG_RTC_M41T11 1 142#define CONFIG_SYS_I2C_RTC_ADDR 0x68 143#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux */ 144 145/*----------------------------------------------------------------------- 146 * PCI stuff 147 *----------------------------------------------------------------------*/ 148#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ 149#define PCI_HOST_FORCE 1 /* configure as pci host */ 150#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ 151 152#undef CONFIG_PCI /* include pci support */ 153#ifdef CONFIG_PCI 154#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */ 155#define CONFIG_PCI_PNP /* do pci plug-and-play */ 156#define CONFIG_PCI_SCAN_SHOW /* show devices on bus */ 157#endif /* CONFIG_PCI */ 158 159/* PCI MEMORY MAP section */ 160#define CONFIG_SYS_PCI0_MEM_BASE 0x80000000 161#define CONFIG_SYS_PCI0_MEM_SIZE _128M 162#define CONFIG_SYS_PCI1_MEM_BASE 0x88000000 163#define CONFIG_SYS_PCI1_MEM_SIZE _128M 164 165#define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE) 166#define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE) 167 168/* PCI I/O MAP section */ 169#define CONFIG_SYS_PCI0_IO_BASE 0xfa000000 170#define CONFIG_SYS_PCI0_IO_SIZE _16M 171#define CONFIG_SYS_PCI1_IO_BASE 0xfb000000 172#define CONFIG_SYS_PCI1_IO_SIZE _16M 173 174#define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE) 175#define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000 176#define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE) 177#define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000 178 179#define CONFIG_SYS_ISA_IO_BASE_ADDRESS (CONFIG_SYS_PCI0_IO_BASE) 180#define CONFIG_SYS_PCI_IDSEL 0x30 181 182#undef CONFIG_BOOTARGS 183#define CONFIG_EXTRA_ENV_SETTINGS_COMMON \ 184 "netdev=eth0\0" \ 185 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 186 "nfsroot=${serverip}:${rootpath}\0" \ 187 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 188 "addip=setenv bootargs ${bootargs} " \ 189 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 190 ":${hostname}:${netdev}:off panic=1\0" \ 191 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ 192 "flash_nfs=run nfsargs addip addtty;" \ 193 "bootm ${kernel_addr}\0" \ 194 "flash_self=run ramargs addip addtty;" \ 195 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 196 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ 197 "bootm\0" \ 198 "rootpath=/opt/eldk/ppc_6xx\0" \ 199 "u-boot=p3mx/u-boot/u-boot.bin\0" \ 200 "load=tftp 100000 ${u-boot}\0" \ 201 "update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \ 202 "cp.b 100000 fff00000 40000;" \ 203 "setenv filesize;saveenv\0" \ 204 "upd=run load update\0" \ 205 "serverip=11.0.0.152\0" 206 207#if defined (CONFIG_P3M750) 208#define CONFIG_EXTRA_ENV_SETTINGS \ 209 CONFIG_EXTRA_ENV_SETTINGS_COMMON \ 210 "hostname=p3m750\0" \ 211 "bootfile=/tftpboot/p3mx/vxWorks.st\0" \ 212 "kernel_addr=fc000000\0" \ 213 "ramdisk_addr=fc180000\0" \ 214 "vxfile=p3m750/vxWorks\0" \ 215 "vxuser=ddg\0" \ 216 "vxpass=ddg\0" \ 217 "vxtarget=target\0" \ 218 "vxflags=0x8\0" \ 219 "vxargs=setenv bootargs mgi(0,0)host:${vxfile} h=${serverip} " \ 220 "e=${ipaddr} u=${vxuser} pw=${vxpass} tn=${vxtarget} " \ 221 "f=${vxflags}\0" 222#elif defined (CONFIG_P3M7448) 223#define CONFIG_EXTRA_ENV_SETTINGS \ 224 CONFIG_EXTRA_ENV_SETTINGS_COMMON \ 225 "hostname=p3m7448\0" 226#endif 227 228#if defined (CONFIG_P3M750) 229#define CONFIG_BOOTCOMMAND "tftp;run vxargs;bootvx" 230#elif defined (CONFIG_P3M7448) 231#define CONFIG_BOOTCOMMAND " " 232#endif 233 234#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ 235 236/* 237 * BOOTP options 238 */ 239#define CONFIG_BOOTP_SUBNETMASK 240#define CONFIG_BOOTP_GATEWAY 241#define CONFIG_BOOTP_HOSTNAME 242#define CONFIG_BOOTP_BOOTPATH 243#define CONFIG_BOOTP_BOOTFILESIZE 244 245/* 246 * Command line configuration. 247 */ 248#include <config_cmd_default.h> 249 250#define CONFIG_CMD_ASKENV 251#define CONFIG_CMD_DATE 252#define CONFIG_CMD_DIAG 253#define CONFIG_CMD_ELF 254#define CONFIG_CMD_I2C 255#define CONFIG_CMD_IRQ 256#define CONFIG_CMD_MII 257#define CONFIG_CMD_NET 258#define CONFIG_CMD_NFS 259#define CONFIG_CMD_PING 260#define CONFIG_CMD_REGINFO 261#define CONFIG_CMD_PCI 262#define CONFIG_CMD_CACHE 263#define CONFIG_CMD_SDRAM 264 265 266/*----------------------------------------------------------------------- 267 * Miscellaneous configurable options 268 *----------------------------------------------------------------------*/ 269#define CONFIG_SYS_HUSH_PARSER 270 271#define CONFIG_SYS_LONGHELP /* undef to save memory */ 272#if defined(CONFIG_CMD_KGDB) 273#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 274#else 275#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 276#endif 277#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 278#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 279#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 280 281#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 282#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 283 284#define CONFIG_SYS_LOAD_ADDR 0x08000000 /* default load address */ 285 286#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 287#define CONFIG_LOOPW 1 /* enable loopw command */ 288#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ 289#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ 290#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ 291 292/*----------------------------------------------------------------------- 293 * Marvell MV64460 config settings 294 *----------------------------------------------------------------------*/ 295/* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected device width */ 296#if defined (CONFIG_P3M750) 297#define CONFIG_SYS_BOOT_PAR 0x8FDFF87F /* 16 bit flash, disable burst*/ 298#elif defined (CONFIG_P3M7448) 299#define CONFIG_SYS_BOOT_PAR 0x8FEFFFFF /* 32 bit flash, burst enabled */ 300#endif 301 302/* 303 * MPP[0] Serial Port 0 TxD TxD OUT Connected to P14 (buffered) 304 * MPP[1] Serial Port 0 RxD RxD IN Connected to P14 (buffered) 305 * MPP[2] NC 306 * MPP[3] Serial Port 1 TxD TxD OUT Connected to P14 (buffered) 307 * MPP[4] PCI Monarch# GPIO IN Connected to P12 308 * MPP[5] Serial Port 1 RxD RxD IN Connected to P14 (buffered) 309 * MPP[6] PMC Carrier Interrupt 0 Int IN Connected to P14 310 * MPP[7] PMC Carrier Interrupt 1 Int IN Connected to P14 311 * MPP[8] Reserved Do not use 312 * MPP[9] Reserved Do not use 313 * MPP[10] Reserved Do not use 314 * MPP[11] Reserved Do not use 315 * MPP[12] Phy 0 Interrupt Int IN 316 * MPP[13] Phy 1 Interrupt Int IN 317 * MPP[14] NC 318 * MPP[15] NC 319 * MPP[16] PCI Interrupt C Int IN Connected to P11 320 * MPP[17] PCI Interrupt D Int IN Connected to P11 321 * MPP[18] Watchdog NMI# GPIO IN Connected to MPP[24] 322 * MPP[19] Watchdog Expired# WDE OUT Connected to rst logic 323 * MPP[20] Watchdog Status WD_STS IN Read back of rst by watchdog 324 * MPP[21] NC 325 * MPP[22] GP LED Green GPIO OUT 326 * MPP[23] GP LED Red GPIO OUT 327 * MPP[24] Watchdog NMI# Int OUT 328 * MPP[25] NC 329 * MPP[26] NC 330 * MPP[27] PCI Interrupt A Int IN Connected to P11 331 * MPP[28] NC 332 * MPP[29] PCI Interrupt B Int IN Connected to P11 333 * MPP[30] Module reset GPIO OUT Board reset 334 * MPP[31] PCI EReady GPIO IN Connected to P12 335 */ 336#define CONFIG_SYS_MPP_CONTROL_0 0x00303022 337#define CONFIG_SYS_MPP_CONTROL_1 0x00000000 338#define CONFIG_SYS_MPP_CONTROL_2 0x00004000 339#define CONFIG_SYS_MPP_CONTROL_3 0x00000004 340#define CONFIG_SYS_GPP_LEVEL_CONTROL 0x280730D0 341 342/*---------------------------------------------------------------------- 343 * Initial BAT mappings 344 */ 345 346/* NOTES: 347 * 1) GUARDED and WRITE_THRU not allowed in IBATS 348 * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT 349 */ 350/* SDRAM */ 351#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 352#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 353#define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT) 354#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U 355 356/* init ram */ 357#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE) 358#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP) 359#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L 360#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U 361 362/* PCI0, PCI1 in one BAT */ 363#define CONFIG_SYS_IBAT2L BATL_NO_ACCESS 364#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U 365#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) 366#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 367 368/* GT regs, bootrom, all the devices, PCI I/O */ 369#define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW) 370#define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M) 371#define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE) 372#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U 373 374#define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) 375#define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP) 376#define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 377#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U 378 379/* set rest out of range for Linux !!!!!!!!!!! */ 380 381/* IBAT5 and DBAT5 */ 382#define CONFIG_SYS_IBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT) 383#define CONFIG_SYS_IBAT5U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP) 384#define CONFIG_SYS_DBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 385#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U 386 387/* IBAT6 and DBAT6 */ 388#define CONFIG_SYS_IBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT) 389#define CONFIG_SYS_IBAT6U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP) 390#define CONFIG_SYS_DBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 391#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U 392 393/* IBAT7 and DBAT7 */ 394#define CONFIG_SYS_IBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT) 395#define CONFIG_SYS_IBAT7U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP) 396#define CONFIG_SYS_DBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) 397#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U 398 399/* 400 * For booting Linux, the board info and command line data 401 * have to be in the first 8 MB of memory, since this is 402 * the maximum mapped by the Linux kernel during initialization. 403 */ 404#define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */ 405#define CONFIG_SYS_VXWORKS_MAC_PTR 0x42010000 /* use some memory in SRAM that's not used!!! */ 406 407/*----------------------------------------------------------------------- 408 * Cache Configuration 409 */ 410#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */ 411#if defined(CONFIG_CMD_KGDB) 412#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 413#endif 414 415/*----------------------------------------------------------------------- 416 * L2CR setup -- make sure this is right for your board! 417 * look in include/mpc74xx.h for the defines used here 418 */ 419#define CONFIG_SYS_L2 420 421#if defined (CONFIG_750CX) || defined (CONFIG_750FX) 422#define L2_INIT 0 423#else 424#define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \ 425 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT) 426#endif 427 428#define L2_ENABLE (L2_INIT | L2CR_L2E) 429 430#ifndef __ASSEMBLY__ 431#include <../board/Marvell/include/core.h> 432#endif 433 434#endif /* __CONFIG_H */ 435