LXR uboot/include/configs/tegra30-common.h

   1/*
   2 *  (C) Copyright 2010-2012
   3 *  NVIDIA Corporation <www.nvidia.com>
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8#ifndef _TEGRA30_COMMON_H_
   9#define _TEGRA30_COMMON_H_
  10#include "tegra-common.h"
  11
  12/* Cortex-A9 uses a cache line size of 32 bytes */
  13#define CONFIG_SYS_CACHELINE_SIZE       32
  14
  15/*
  16 * Errata configuration
  17 */
  18#define CONFIG_ARM_ERRATA_743622
  19#define CONFIG_ARM_ERRATA_751472
  20
  21/*
  22 * NS16550 Configuration
  23 */
  24#define V_NS16550_CLK           408000000       /* 408MHz (pllp_out0) */
  25
  26/* Environment information, boards can override if required */
  27#define CONFIG_LOADADDR         0x80408000      /* def. location for kernel */
  28
  29/*
  30 * Miscellaneous configurable options
  31 */
  32#define CONFIG_SYS_LOAD_ADDR    0x80A00800      /* default */
  33#define CONFIG_STACKBASE        0x82800000      /* 40MB */
  34
  35/*-----------------------------------------------------------------------
  36 * Physical Memory Map
  37 */
  38#define CONFIG_SYS_TEXT_BASE    0x8010E000
  39
  40/*
  41 * Memory layout for where various images get loaded by boot scripts:
  42 *
  43 * scriptaddr can be pretty much anywhere that doesn't conflict with something
  44 *   else. Put it above BOOTMAPSZ to eliminate conflicts.
  45 *
  46 * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
  47 *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
  48 *
  49 * kernel_addr_r must be within the first 128M of RAM in order for the
  50 *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
  51 *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
  52 *   should not overlap that area, or the kernel will have to copy itself
  53 *   somewhere else before decompression. Similarly, the address of any other
  54 *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
  55 *   this up to 16M allows for a sizable kernel to be decompressed below the
  56 *   compressed load address.
  57 *
  58 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
  59 *   the compressed kernel to be up to 16M too.
  60 *
  61 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
  62 *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
  63 */
  64#define MEM_LAYOUT_ENV_SETTINGS \
  65        "scriptaddr=0x90000000\0" \
  66        "pxefile_addr_r=0x90100000\0" \
  67        "kernel_addr_r=0x81000000\0" \
  68        "fdt_addr_r=0x82000000\0" \
  69        "ramdisk_addr_r=0x82100000\0"
  70
  71/* Defines for SPL */
  72#define CONFIG_SPL_TEXT_BASE            0x80108000
  73#define CONFIG_SYS_SPL_MALLOC_START     0x80090000
  74#define CONFIG_SPL_STACK                0x800ffffc
  75
  76/* Total I2C ports on Tegra30 */
  77#define TEGRA_I2C_NUM_CONTROLLERS       5
  78
  79/* For USB EHCI controller */
  80#define CONFIG_EHCI_IS_TDI
  81#define CONFIG_USB_EHCI_TXFIFO_THRESH   0x10
  82#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
  83
  84#endif /* _TEGRA30_COMMON_H_ */
  85