1/* 2 * (C) Copyright 2003-2006 Wolfgang Denk, DENX Software Engineering, 3 * wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8#ifndef __CONFIG_H 9#define __CONFIG_H 10 11/* 12 * High Level Configuration Options 13 * (easy to change) 14 */ 15#define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ 16#define CONFIG_V38B 1 /* ...on V38B board */ 17 18#define CONFIG_SYS_TEXT_BASE 0xFF000000 19 20#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ...running at 33.000000MHz */ 21 22#define CONFIG_RTC_PCF8563 1 /* has PCF8563 RTC */ 23#define CONFIG_MPC5200_DDR 1 /* has DDR SDRAM */ 24 25#undef CONFIG_HW_WATCHDOG /* don't use watchdog */ 26 27#define CONFIG_NETCONSOLE 1 28 29#define CONFIG_BOARD_EARLY_INIT_R 1 /* do board-specific init */ 30#define CONFIG_BOARD_EARLY_INIT_F 1 /* do board-specific init */ 31#define CONFIG_MISC_INIT_R 32 33#define CONFIG_SYS_XLB_PIPELINING 1 /* gives better performance */ 34 35#define CONFIG_HIGH_BATS 1 /* High BATs supported */ 36 37/* 38 * Serial console configuration 39 */ 40#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ 41#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ 42#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } 43 44/* 45 * DDR 46 */ 47#define SDRAM_DDR 1 /* is DDR */ 48/* Settings for XLB = 132 MHz */ 49#define SDRAM_MODE 0x018D0000 50#define SDRAM_EMODE 0x40090000 51#define SDRAM_CONTROL 0x704f0f00 52#define SDRAM_CONFIG1 0x73722930 53#define SDRAM_CONFIG2 0x47770000 54#define SDRAM_TAPDELAY 0x10000000 55 56/* 57 * PCI - no suport 58 */ 59#undef CONFIG_PCI 60 61/* 62 * Partitions 63 */ 64#define CONFIG_MAC_PARTITION 1 65#define CONFIG_DOS_PARTITION 1 66 67/* 68 * USB 69 */ 70#define CONFIG_USB_OHCI 71#define CONFIG_USB_STORAGE 72#define CONFIG_USB_CLOCK 0x0001BBBB 73#define CONFIG_USB_CONFIG 0x00001000 74 75 76/* 77 * BOOTP options 78 */ 79#define CONFIG_BOOTP_BOOTFILESIZE 80#define CONFIG_BOOTP_BOOTPATH 81#define CONFIG_BOOTP_GATEWAY 82#define CONFIG_BOOTP_HOSTNAME 83 84 85/* 86 * Command line configuration. 87 */ 88#include <config_cmd_default.h> 89 90#define CONFIG_CMD_FAT 91#define CONFIG_CMD_I2C 92#define CONFIG_CMD_IDE 93#define CONFIG_CMD_PING 94#define CONFIG_CMD_DHCP 95#define CONFIG_CMD_DIAG 96#define CONFIG_CMD_IRQ 97#define CONFIG_CMD_JFFS2 98#define CONFIG_CMD_MII 99#define CONFIG_CMD_SDRAM 100#define CONFIG_CMD_DATE 101#define CONFIG_CMD_USB 102#define CONFIG_CMD_FAT 103 104 105#define CONFIG_TIMESTAMP /* Print image info with timestamp */ 106 107/* 108 * Boot low with 16 MB Flash 109 */ 110#define CONFIG_SYS_LOWBOOT 1 111#define CONFIG_SYS_LOWBOOT16 1 112 113/* 114 * Autobooting 115 */ 116#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ 117 118#define CONFIG_PREBOOT "echo;" \ 119 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 120 "echo" 121 122#undef CONFIG_BOOTARGS 123 124#define CONFIG_EXTRA_ENV_SETTINGS \ 125 "bootcmd=run net_nfs\0" \ 126 "bootdelay=3\0" \ 127 "baudrate=115200\0" \ 128 "preboot=echo;echo Type \"run flash_nfs\" to mount root " \ 129 "filesystem over NFS; echo\0" \ 130 "netdev=eth0\0" \ 131 "ramargs=setenv bootargs root=/dev/ram rw wdt=off \0" \ 132 "addip=setenv bootargs $(bootargs) " \ 133 "ip=$(ipaddr):$(serverip):$(gatewayip):" \ 134 "$(netmask):$(hostname):$(netdev):off panic=1\0" \ 135 "flash_nfs=run nfsargs addip;bootm $(kernel_addr)\0" \ 136 "flash_self=run ramargs addip;bootm $(kernel_addr) " \ 137 "$(ramdisk_addr)\0" \ 138 "net_nfs=tftp 200000 $(bootfile);run nfsargs addip;bootm\0" \ 139 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 140 "nfsroot=$(serverip):$(rootpath) wdt=off\0" \ 141 "hostname=v38b\0" \ 142 "ethact=FEC\0" \ 143 "rootpath=/opt/eldk-3.1.1/ppc_6xx\0" \ 144 "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \ 145 "cp.b 200000 ff000000 $(filesize);" \ 146 "prot on ff000000 ff03ffff\0" \ 147 "load=tftp 200000 $(u-boot)\0" \ 148 "netmask=255.255.0.0\0" \ 149 "ipaddr=192.168.160.18\0" \ 150 "serverip=192.168.1.1\0" \ 151 "ethaddr=00:e0:ee:00:05:2e\0" \ 152 "bootfile=/tftpboot/v38b/uImage\0" \ 153 "u-boot=/tftpboot/v38b/u-boot.bin\0" \ 154 "" 155 156#define CONFIG_BOOTCOMMAND "run net_nfs" 157 158/* 159 * IPB Bus clocking configuration. 160 */ 161#undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ 162 163/* 164 * I2C configuration 165 */ 166#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ 167#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */ 168#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ 169#define CONFIG_SYS_I2C_SLAVE 0x7F 170 171/* 172 * EEPROM configuration 173 */ 174#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ 175#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 176#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 177#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70 178 179/* 180 * RTC configuration 181 */ 182#define CONFIG_SYS_I2C_RTC_ADDR 0x51 183 184/* 185 * Flash configuration - use CFI driver 186 */ 187#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 188#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 189#define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 190#define CONFIG_SYS_FLASH_BASE 0xFF000000 191#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */ 192#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 193#define CONFIG_SYS_FLASH_SIZE 0x01000000 /* 16 MiB */ 194#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ 195#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* flash write speed-up */ 196 197/* 198 * Environment settings 199 */ 200#define CONFIG_ENV_IS_IN_FLASH 1 201#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000) 202#define CONFIG_ENV_SIZE 0x10000 203#define CONFIG_ENV_SECT_SIZE 0x10000 204#define CONFIG_ENV_OVERWRITE 1 205 206/* 207 * Memory map 208 */ 209#define CONFIG_SYS_MBAR 0xF0000000 210#define CONFIG_SYS_SDRAM_BASE 0x00000000 211#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 212 213/* Use SRAM until RAM will be available */ 214#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM 215#define CONFIG_SYS_INIT_RAM_SIZE MPC5XXX_SRAM_SIZE /* Size of used area in DPRAM */ 216 217#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 218#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 219 220#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE 221#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) 222# define CONFIG_SYS_RAMBOOT 1 223#endif 224 225#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256kB for Monitor */ 226#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128kB for malloc() */ 227#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Linux initial memory map */ 228 229/* 230 * Ethernet configuration 231 */ 232#define CONFIG_MPC5xxx_FEC 1 233#define CONFIG_MPC5xxx_FEC_MII100 234#define CONFIG_PHY_ADDR 0x00 235#define CONFIG_MII 1 236 237/* 238 * GPIO configuration 239 */ 240#define CONFIG_SYS_GPS_PORT_CONFIG 0x90001404 241 242/* 243 * Miscellaneous configurable options 244 */ 245#define CONFIG_SYS_LONGHELP /* undef to save memory */ 246#if defined(CONFIG_CMD_KGDB) 247#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 248#else 249#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 250#endif 251#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 252#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 253#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 254 255#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ 256#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ 257 258#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 259 260#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ 261#if defined(CONFIG_CMD_KGDB) 262# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ 263#endif 264 265/* 266 * Various low-level settings 267 */ 268#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI 269#define CONFIG_SYS_HID0_FINAL HID0_ICE 270 271#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE 272#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE 273#define CONFIG_SYS_BOOTCS_CFG 0x00047801 274#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE 275#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE 276 277#define CONFIG_SYS_CS_BURST 0x00000000 278#define CONFIG_SYS_CS_DEADCYCLE 0x33333333 279 280#define CONFIG_SYS_RESET_ADDRESS 0xff000000 281 282/* 283 * IDE/ATA (supports IDE harddisk) 284 */ 285#undef CONFIG_IDE_8xx_PCCARD /* Don't use IDE with PC Card Adapter */ 286#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 287#undef CONFIG_IDE_LED /* LED for ide not supported */ 288 289#define CONFIG_IDE_RESET /* reset for ide supported */ 290#define CONFIG_IDE_PREINIT 291 292#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 293#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 294 295#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 296 297#define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA 298 299#define CONFIG_SYS_ATA_DATA_OFFSET (0x0060) /* data I/O offset */ 300 301#define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* normal register accesses offset */ 302 303#define CONFIG_SYS_ATA_ALT_OFFSET (0x005C) /* alternate registers offset */ 304 305#define CONFIG_SYS_ATA_STRIDE 4 /* Interval between registers */ 306 307/* 308 * Status LED 309 */ 310#define CONFIG_STATUS_LED /* Status LED enabled */ 311#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ 312 313#define CONFIG_SYS_LED_BASE MPC5XXX_GPT7_ENABLE /* Timer 7 GPIO */ 314#ifndef __ASSEMBLY__ 315typedef unsigned int led_id_t; 316 317#define __led_toggle(_msk) \ 318 do { \ 319 *((volatile long *) (CONFIG_SYS_LED_BASE)) ^= (_msk); \ 320 } while(0) 321 322#define __led_set(_msk, _st) \ 323 do { \ 324 if ((_st)) \ 325 *((volatile long *) (CONFIG_SYS_LED_BASE)) &= ~(_msk); \ 326 else \ 327 *((volatile long *) (CONFIG_SYS_LED_BASE)) |= (_msk); \ 328 } while(0) 329 330#define __led_init(_msk, st) \ 331 do { \ 332 *((volatile long *) (CONFIG_SYS_LED_BASE)) |= 0x34; \ 333 } while(0) 334#endif /* __ASSEMBLY__ */ 335 336#endif /* __CONFIG_H */ 337