1/* 2 * Copyright (C) 2012 Samsung Electronics 3 * 4 * Author: Donghwa Lee <dh09.lee@samsung.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9#ifndef __ASM_ARM_ARCH_DP_H_ 10#define __ASM_ARM_ARCH_DP_H_ 11 12#ifndef __ASSEMBLY__ 13 14struct exynos_dp { 15 unsigned char res1[0x10]; 16 unsigned int tx_version; 17 unsigned int tx_sw_reset; 18 unsigned int func_en1; 19 unsigned int func_en2; 20 unsigned int video_ctl1; 21 unsigned int video_ctl2; 22 unsigned int video_ctl3; 23 unsigned int video_ctl4; 24 unsigned int color_blue_cb; 25 unsigned int color_green_y; 26 unsigned int color_red_cr; 27 unsigned int video_ctl8; 28 unsigned char res2[0x4]; 29 unsigned int video_ctl10; 30 unsigned int total_ln_cfg_l; 31 unsigned int total_ln_cfg_h; 32 unsigned int active_ln_cfg_l; 33 unsigned int active_ln_cfg_h; 34 unsigned int vfp_cfg; 35 unsigned int vsw_cfg; 36 unsigned int vbp_cfg; 37 unsigned int total_pix_cfg_l; 38 unsigned int total_pix_cfg_h; 39 unsigned int active_pix_cfg_l; 40 unsigned int active_pix_cfg_h; 41 unsigned int hfp_cfg_l; 42 unsigned int hfp_cfg_h; 43 unsigned int hsw_cfg_l; 44 unsigned int hsw_cfg_h; 45 unsigned int hbp_cfg_l; 46 unsigned int hbp_cfg_h; 47 unsigned int video_status; 48 unsigned int total_ln_sta_l; 49 unsigned int total_ln_sta_h; 50 unsigned int active_ln_sta_l; 51 unsigned int active_ln_sta_h; 52 53 unsigned int vfp_sta; 54 unsigned int vsw_sta; 55 unsigned int vbp_sta; 56 57 unsigned int total_pix_sta_l; 58 unsigned int total_pix_sta_h; 59 unsigned int active_pix_sta_l; 60 unsigned int active_pix_sta_h; 61 62 unsigned int hfp_sta_l; 63 unsigned int hfp_sta_h; 64 unsigned int hsw_sta_l; 65 unsigned int hsw_sta_h; 66 unsigned int hbp_sta_l; 67 unsigned int hbp_sta_h; 68 69 unsigned char res3[0x288]; 70 71 unsigned int lane_map; 72 unsigned char res4[0x10]; 73 unsigned int analog_ctl1; 74 unsigned int analog_ctl2; 75 unsigned int analog_ctl3; 76 77 unsigned int pll_filter_ctl1; 78 unsigned int amp_tuning_ctl; 79 unsigned char res5[0xc]; 80 81 unsigned int aux_hw_retry_ctl; 82 unsigned char res6[0x2c]; 83 unsigned int int_state; 84 unsigned int common_int_sta1; 85 unsigned int common_int_sta2; 86 unsigned int common_int_sta3; 87 unsigned int common_int_sta4; 88 unsigned char res7[0x8]; 89 90 unsigned int int_sta; 91 unsigned char res8[0x1c]; 92 unsigned int int_ctl; 93 unsigned char res9[0x200]; 94 unsigned int sys_ctl1; 95 unsigned int sys_ctl2; 96 unsigned int sys_ctl3; 97 unsigned int sys_ctl4; 98 unsigned int vid_ctl; 99 unsigned char res10[0x2c]; 100 unsigned int pkt_send_ctl; 101 unsigned char res[0x4]; 102 unsigned int hdcp_ctl; 103 unsigned char res11[0x34]; 104 unsigned int link_bw_set; 105 106 unsigned int lane_count_set; 107 unsigned int training_ptn_set; 108 unsigned int ln0_link_training_ctl; 109 unsigned int ln1_link_training_ctl; 110 unsigned int ln2_link_training_ctl; 111 unsigned int ln3_link_training_ctl; 112 unsigned int dn_spread_ctl; 113 unsigned int hw_link_training_ctl; 114 unsigned char res12[0x1c]; 115 116 unsigned int debug_ctl; 117 unsigned int hpd_deglitch_l; 118 unsigned int hpd_deglitch_h; 119 120 unsigned char res13[0x14]; 121 unsigned int link_debug_ctl; 122 123 unsigned char res14[0x1c]; 124 125 unsigned int m_vid0; 126 unsigned int m_vid1; 127 unsigned int m_vid2; 128 unsigned int n_vid0; 129 unsigned int n_vid1; 130 unsigned int n_vid2; 131 unsigned int m_vid_mon; 132 unsigned int pll_ctl; 133 unsigned int phy_pd; 134 unsigned int phy_test; 135 unsigned char res15[0x8]; 136 137 unsigned int video_fifo_thrd; 138 unsigned char res16[0x8]; 139 unsigned int audio_margin; 140 141 unsigned int dn_spread_ctl1; 142 unsigned int dn_spread_ctl2; 143 unsigned char res17[0x18]; 144 unsigned int m_cal_ctl; 145 unsigned int m_vid_gen_filter_th; 146 unsigned char res18[0x10]; 147 unsigned int m_aud_gen_filter_th; 148 unsigned char res50[0x4]; 149 150 unsigned int aux_ch_sta; 151 unsigned int aux_err_num; 152 unsigned int aux_ch_defer_ctl; 153 unsigned int aux_rx_comm; 154 unsigned int buffer_data_ctl; 155 156 unsigned int aux_ch_ctl1; 157 unsigned int aux_addr_7_0; 158 unsigned int aux_addr_15_8; 159 unsigned int aux_addr_19_16; 160 unsigned int aux_ch_ctl2; 161 unsigned char res19[0x18]; 162 unsigned int buf_data0; 163 unsigned char res20[0x3c]; 164 165 unsigned int soc_general_ctl; 166 unsigned char res21[0x8c]; 167 unsigned int crc_con; 168 unsigned int crc_result; 169 unsigned char res22[0x8]; 170 171 unsigned int common_int_mask1; 172 unsigned int common_int_mask2; 173 unsigned int common_int_mask3; 174 unsigned int common_int_mask4; 175 unsigned int int_sta_mask1; 176 unsigned int int_sta_mask2; 177 unsigned int int_sta_mask3; 178 unsigned int int_sta_mask4; 179 unsigned int int_sta_mask; 180 unsigned int crc_result2; 181 unsigned int scrambler_reset_cnt; 182 183 unsigned int pn_inv; 184 unsigned int psr_config; 185 unsigned int psr_command0; 186 unsigned int psr_command1; 187 unsigned int psr_crc_mon0; 188 unsigned int psr_crc_mon1; 189 190 unsigned char res24[0x30]; 191 unsigned int phy_bist_ctrl; 192 unsigned char res25[0xc]; 193 unsigned int phy_ctrl; 194 unsigned char res26[0x1c]; 195 unsigned int test_pattern_gen_en; 196 unsigned int test_pattern_gen_ctrl; 197}; 198 199#endif /* __ASSEMBLY__ */ 200 201/* For DP VIDEO CTL 1 */ 202#define VIDEO_EN_MASK (0x01 << 7) 203#define VIDEO_MUTE_MASK (0x01 << 6) 204 205/* For DP VIDEO CTL 4 */ 206#define VIDEO_BIST_MASK (0x1 << 3) 207 208/* EXYNOS_DP_ANALOG_CTL_1 */ 209#define SEL_BG_NEW_BANDGAP (0x0 << 6) 210#define SEL_BG_INTERNAL_RESISTOR (0x1 << 6) 211#define TX_TERMINAL_CTRL_73_OHM (0x0 << 4) 212#define TX_TERMINAL_CTRL_61_OHM (0x1 << 4) 213#define TX_TERMINAL_CTRL_50_OHM (0x2 << 4) 214#define TX_TERMINAL_CTRL_45_OHM (0x3 << 4) 215#define SWING_A_30PER_G_INCREASE (0x1 << 3) 216#define SWING_A_30PER_G_NORMAL (0x0 << 3) 217 218/* EXYNOS_DP_ANALOG_CTL_2 */ 219#define CPREG_BLEED (0x1 << 4) 220#define SEL_24M (0x1 << 3) 221#define TX_DVDD_BIT_1_0000V (0x3 << 0) 222#define TX_DVDD_BIT_1_0625V (0x4 << 0) 223#define TX_DVDD_BIT_1_1250V (0x5 << 0) 224 225/* EXYNOS_DP_ANALOG_CTL_3 */ 226#define DRIVE_DVDD_BIT_1_0000V (0x3 << 5) 227#define DRIVE_DVDD_BIT_1_0625V (0x4 << 5) 228#define DRIVE_DVDD_BIT_1_1250V (0x5 << 5) 229#define SEL_CURRENT_DEFAULT (0x0 << 3) 230#define VCO_BIT_000_MICRO (0x0 << 0) 231#define VCO_BIT_200_MICRO (0x1 << 0) 232#define VCO_BIT_300_MICRO (0x2 << 0) 233#define VCO_BIT_400_MICRO (0x3 << 0) 234#define VCO_BIT_500_MICRO (0x4 << 0) 235#define VCO_BIT_600_MICRO (0x5 << 0) 236#define VCO_BIT_700_MICRO (0x6 << 0) 237#define VCO_BIT_900_MICRO (0x7 << 0) 238 239/* EXYNOS_DP_PLL_FILTER_CTL_1 */ 240#define PD_RING_OSC (0x1 << 6) 241#define AUX_TERMINAL_CTRL_52_OHM (0x3 << 4) 242#define AUX_TERMINAL_CTRL_69_OHM (0x2 << 4) 243#define AUX_TERMINAL_CTRL_102_OHM (0x1 << 4) 244#define AUX_TERMINAL_CTRL_200_OHM (0x0 << 4) 245#define TX_CUR1_1X (0x0 << 2) 246#define TX_CUR1_2X (0x1 << 2) 247#define TX_CUR1_3X (0x2 << 2) 248#define TX_CUR_1_MA (0x0 << 0) 249#define TX_CUR_2_MA (0x1 << 0) 250#define TX_CUR_3_MA (0x2 << 0) 251#define TX_CUR_4_MA (0x3 << 0) 252 253/* EXYNOS_DP_PLL_FILTER_CTL_2 */ 254#define CH3_AMP_0_MV (0x3 << 12) 255#define CH2_AMP_0_MV (0x3 << 8) 256#define CH1_AMP_0_MV (0x3 << 4) 257#define CH0_AMP_0_MV (0x3 << 0) 258 259/* EXYNOS_DP_PLL_CTL */ 260#define DP_PLL_PD (0x1 << 7) 261#define DP_PLL_RESET (0x1 << 6) 262#define DP_PLL_LOOP_BIT_DEFAULT (0x1 << 4) 263#define DP_PLL_REF_BIT_1_1250V (0x5 << 0) 264#define DP_PLL_REF_BIT_1_2500V (0x7 << 0) 265 266/* EXYNOS_DP_INT_CTL */ 267#define SOFT_INT_CTRL (0x1 << 2) 268#define INT_POL (0x1 << 0) 269 270/* DP TX SW RESET */ 271#define RESET_DP_TX (0x01 << 0) 272 273/* DP FUNC_EN_1 */ 274#define MASTER_VID_FUNC_EN_N (0x1 << 7) 275#define SLAVE_VID_FUNC_EN_N (0x1 << 5) 276#define AUD_FIFO_FUNC_EN_N (0x1 << 4) 277#define AUD_FUNC_EN_N (0x1 << 3) 278#define HDCP_FUNC_EN_N (0x1 << 2) 279#define CRC_FUNC_EN_N (0x1 << 1) 280#define SW_FUNC_EN_N (0x1 << 0) 281 282/* DP FUNC_EN_2 */ 283#define SSC_FUNC_EN_N (0x1 << 7) 284#define AUX_FUNC_EN_N (0x1 << 2) 285#define SERDES_FIFO_FUNC_EN_N (0x1 << 1) 286#define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0) 287 288/* EXYNOS_DP_PHY_PD */ 289#define PHY_PD (0x1 << 5) 290#define AUX_PD (0x1 << 4) 291#define CH3_PD (0x1 << 3) 292#define CH2_PD (0x1 << 2) 293#define CH1_PD (0x1 << 1) 294#define CH0_PD (0x1 << 0) 295 296/* EXYNOS_DP_COMMON_INT_STA_1 */ 297#define VSYNC_DET (0x1 << 7) 298#define PLL_LOCK_CHG (0x1 << 6) 299#define SPDIF_ERR (0x1 << 5) 300#define SPDIF_UNSTBL (0x1 << 4) 301#define VID_FORMAT_CHG (0x1 << 3) 302#define AUD_CLK_CHG (0x1 << 2) 303#define VID_CLK_CHG (0x1 << 1) 304#define SW_INT (0x1 << 0) 305 306/* EXYNOS_DP_DEBUG_CTL */ 307#define PLL_LOCK (0x1 << 4) 308#define F_PLL_LOCK (0x1 << 3) 309#define PLL_LOCK_CTRL (0x1 << 2) 310 311/* EXYNOS_DP_FUNC_EN_2 */ 312#define SSC_FUNC_EN_N (0x1 << 7) 313#define AUX_FUNC_EN_N (0x1 << 2) 314#define SERDES_FIFO_FUNC_EN_N (0x1 << 1) 315#define LS_CLK_DOMAIN_FUNC_EN_N (0x1 << 0) 316 317/* EXYNOS_DP_COMMON_INT_STA_4 */ 318#define PSR_ACTIVE (0x1 << 7) 319#define PSR_INACTIVE (0x1 << 6) 320#define SPDIF_BI_PHASE_ERR (0x1 << 5) 321#define HOTPLUG_CHG (0x1 << 2) 322#define HPD_LOST (0x1 << 1) 323#define PLUG (0x1 << 0) 324 325/* EXYNOS_DP_INT_STA */ 326#define INT_HPD (0x1 << 6) 327#define HW_TRAINING_FINISH (0x1 << 5) 328#define RPLY_RECEIV (0x1 << 1) 329#define AUX_ERR (0x1 << 0) 330 331/* EXYNOS_DP_SYS_CTL_3 */ 332#define HPD_STATUS (0x1 << 6) 333#define F_HPD (0x1 << 5) 334#define HPD_CTRL (0x1 << 4) 335#define HDCP_RDY (0x1 << 3) 336#define STRM_VALID (0x1 << 2) 337#define F_VALID (0x1 << 1) 338#define VALID_CTRL (0x1 << 0) 339 340/* EXYNOS_DP_AUX_HW_RETRY_CTL */ 341#define AUX_BIT_PERIOD_EXPECTED_DELAY(x) (((x) & 0x7) << 8) 342#define AUX_HW_RETRY_INTERVAL_MASK (0x3 << 3) 343#define AUX_HW_RETRY_INTERVAL_600_MICROSECONDS (0x0 << 3) 344#define AUX_HW_RETRY_INTERVAL_800_MICROSECONDS (0x1 << 3) 345#define AUX_HW_RETRY_INTERVAL_1000_MICROSECONDS (0x2 << 3) 346#define AUX_HW_RETRY_INTERVAL_1800_MICROSECONDS (0x3 << 3) 347#define AUX_HW_RETRY_COUNT_SEL(x) (((x) & 0x7) << 0) 348 349/* EXYNOS_DP_AUX_CH_DEFER_CTL */ 350#define DEFER_CTRL_EN (0x1 << 7) 351#define DEFER_COUNT(x) (((x) & 0x7f) << 0) 352 353#define COMMON_INT_MASK_1 (0) 354#define COMMON_INT_MASK_2 (0) 355#define COMMON_INT_MASK_3 (0) 356#define COMMON_INT_MASK_4 (0) 357#define INT_STA_MASK (0) 358 359/* EXYNOS_DP_BUFFER_DATA_CTL */ 360#define BUF_CLR (0x1 << 7) 361#define BUF_DATA_COUNT(x) (((x) & 0x1f) << 0) 362 363/* EXYNOS_DP_AUX_ADDR_7_0 */ 364#define AUX_ADDR_7_0(x) (((x) >> 0) & 0xff) 365 366/* EXYNOS_DP_AUX_ADDR_15_8 */ 367#define AUX_ADDR_15_8(x) (((x) >> 8) & 0xff) 368 369/* EXYNOS_DP_AUX_ADDR_19_16 */ 370#define AUX_ADDR_19_16(x) (((x) >> 16) & 0x0f) 371 372/* EXYNOS_DP_AUX_CH_CTL_1 */ 373#define AUX_LENGTH(x) (((x - 1) & 0xf) << 4) 374#define AUX_TX_COMM_MASK (0xf << 0) 375#define AUX_TX_COMM_DP_TRANSACTION (0x1 << 3) 376#define AUX_TX_COMM_I2C_TRANSACTION (0x0 << 3) 377#define AUX_TX_COMM_MOT (0x1 << 2) 378#define AUX_TX_COMM_WRITE (0x0 << 0) 379#define AUX_TX_COMM_READ (0x1 << 0) 380 381/* EXYNOS_DP_AUX_CH_CTL_2 */ 382#define ADDR_ONLY (0x1 << 1) 383#define AUX_EN (0x1 << 0) 384 385/* EXYNOS_DP_AUX_CH_STA */ 386#define AUX_BUSY (0x1 << 4) 387#define AUX_STATUS_MASK (0xf << 0) 388 389/* EXYNOS_DP_AUX_RX_COMM */ 390#define AUX_RX_COMM_I2C_DEFER (0x2 << 2) 391#define AUX_RX_COMM_AUX_DEFER (0x2 << 0) 392 393/* EXYNOS_DP_PHY_TEST */ 394#define MACRO_RST (0x1 << 5) 395#define CH1_TEST (0x1 << 1) 396#define CH0_TEST (0x1 << 0) 397 398/* EXYNOS_DP_TRAINING_PTN_SET */ 399#define SCRAMBLER_TYPE (0x1 << 9) 400#define HW_LINK_TRAINING_PATTERN (0x1 << 8) 401#define SCRAMBLING_DISABLE (0x1 << 5) 402#define SCRAMBLING_ENABLE (0x0 << 5) 403#define LINK_QUAL_PATTERN_SET_MASK (0x3 << 2) 404#define LINK_QUAL_PATTERN_SET_PRBS7 (0x3 << 2) 405#define LINK_QUAL_PATTERN_SET_D10_2 (0x1 << 2) 406#define LINK_QUAL_PATTERN_SET_DISABLE (0x0 << 2) 407#define SW_TRAINING_PATTERN_SET_MASK (0x3 << 0) 408#define SW_TRAINING_PATTERN_SET_PTN2 (0x2 << 0) 409#define SW_TRAINING_PATTERN_SET_PTN1 (0x1 << 0) 410#define SW_TRAINING_PATTERN_SET_NORMAL (0x0 << 0) 411 412/* EXYNOS_DP_TOTAL_LINE_CFG */ 413#define TOTAL_LINE_CFG_L(x) ((x) & 0xff) 414#define TOTAL_LINE_CFG_H(x) ((((x) >> 8)) & 0xff) 415#define ACTIVE_LINE_CFG_L(x) ((x) & 0xff) 416#define ACTIVE_LINE_CFG_H(x) (((x) >> 8) & 0xff) 417#define TOTAL_PIXEL_CFG_L(x) ((x) & 0xff) 418#define TOTAL_PIXEL_CFG_H(x) ((((x) >> 8)) & 0xff) 419#define ACTIVE_PIXEL_CFG_L(x) ((x) & 0xff) 420#define ACTIVE_PIXEL_CFG_H(x) ((((x) >> 8)) & 0xff) 421 422#define H_F_PORCH_CFG_L(x) ((x) & 0xff) 423#define H_F_PORCH_CFG_H(x) ((((x) >> 8)) & 0xff) 424#define H_SYNC_PORCH_CFG_L(x) ((x) & 0xff) 425#define H_SYNC_PORCH_CFG_H(x) ((((x) >> 8)) & 0xff) 426#define H_B_PORCH_CFG_L(x) ((x) & 0xff) 427#define H_B_PORCH_CFG_H(x) ((((x) >> 8)) & 0xff) 428 429/* EXYNOS_DP_LN0_LINK_TRAINING_CTL */ 430#define MAX_PRE_EMPHASIS_REACH_0 (0x1 << 5) 431#define PRE_EMPHASIS_SET_0_SET(x) (((x) & 0x3) << 3) 432#define PRE_EMPHASIS_SET_0_GET(x) (((x) >> 3) & 0x3) 433#define PRE_EMPHASIS_SET_0_MASK (0x3 << 3) 434#define PRE_EMPHASIS_SET_0_SHIFT (3) 435#define PRE_EMPHASIS_SET_0_LEVEL_3 (0x3 << 3) 436#define PRE_EMPHASIS_SET_0_LEVEL_2 (0x2 << 3) 437#define PRE_EMPHASIS_SET_0_LEVEL_1 (0x1 << 3) 438#define PRE_EMPHASIS_SET_0_LEVEL_0 (0x0 << 3) 439#define MAX_DRIVE_CURRENT_REACH_0 (0x1 << 2) 440#define DRIVE_CURRENT_SET_0_MASK (0x3 << 0) 441#define DRIVE_CURRENT_SET_0_SET(x) (((x) & 0x3) << 0) 442#define DRIVE_CURRENT_SET_0_GET(x) (((x) >> 0) & 0x3) 443#define DRIVE_CURRENT_SET_0_LEVEL_3 (0x3 << 0) 444#define DRIVE_CURRENT_SET_0_LEVEL_2 (0x2 << 0) 445#define DRIVE_CURRENT_SET_0_LEVEL_1 (0x1 << 0) 446#define DRIVE_CURRENT_SET_0_LEVEL_0 (0x0 << 0) 447 448/* EXYNOS_DP_LN1_LINK_TRAINING_CTL */ 449#define MAX_PRE_EMPHASIS_REACH_1 (0x1 << 5) 450#define PRE_EMPHASIS_SET_1_SET(x) (((x) & 0x3) << 3) 451#define PRE_EMPHASIS_SET_1_GET(x) (((x) >> 3) & 0x3) 452#define PRE_EMPHASIS_SET_1_MASK (0x3 << 3) 453#define PRE_EMPHASIS_SET_1_SHIFT (3) 454#define PRE_EMPHASIS_SET_1_LEVEL_3 (0x3 << 3) 455#define PRE_EMPHASIS_SET_1_LEVEL_2 (0x2 << 3) 456#define PRE_EMPHASIS_SET_1_LEVEL_1 (0x1 << 3) 457#define PRE_EMPHASIS_SET_1_LEVEL_0 (0x0 << 3) 458#define MAX_DRIVE_CURRENT_REACH_1 (0x1 << 2) 459#define DRIVE_CURRENT_SET_1_MASK (0x3 << 0) 460#define DRIVE_CURRENT_SET_1_SET(x) (((x) & 0x3) << 0) 461#define DRIVE_CURRENT_SET_1_GET(x) (((x) >> 0) & 0x3) 462#define DRIVE_CURRENT_SET_1_LEVEL_3 (0x3 << 0) 463#define DRIVE_CURRENT_SET_1_LEVEL_2 (0x2 << 0) 464#define DRIVE_CURRENT_SET_1_LEVEL_1 (0x1 << 0) 465#define DRIVE_CURRENT_SET_1_LEVEL_0 (0x0 << 0) 466 467/* EXYNOS_DP_LN2_LINK_TRAINING_CTL */ 468#define MAX_PRE_EMPHASIS_REACH_2 (0x1 << 5) 469#define PRE_EMPHASIS_SET_2_SET(x) (((x) & 0x3) << 3) 470#define PRE_EMPHASIS_SET_2_GET(x) (((x) >> 3) & 0x3) 471#define PRE_EMPHASIS_SET_2_MASK (0x3 << 3) 472#define PRE_EMPHASIS_SET_2_SHIFT (3) 473#define PRE_EMPHASIS_SET_2_LEVEL_3 (0x3 << 3) 474#define PRE_EMPHASIS_SET_2_LEVEL_2 (0x2 << 3) 475#define PRE_EMPHASIS_SET_2_LEVEL_1 (0x1 << 3) 476#define PRE_EMPHASIS_SET_2_LEVEL_0 (0x0 << 3) 477#define MAX_DRIVE_CURRENT_REACH_2 (0x1 << 2) 478#define DRIVE_CURRENT_SET_2_MASK (0x3 << 0) 479#define DRIVE_CURRENT_SET_2_SET(x) (((x) & 0x3) << 0) 480#define DRIVE_CURRENT_SET_2_GET(x) (((x) >> 0) & 0x3) 481#define DRIVE_CURRENT_SET_2_LEVEL_3 (0x3 << 0) 482#define DRIVE_CURRENT_SET_2_LEVEL_2 (0x2 << 0) 483#define DRIVE_CURRENT_SET_2_LEVEL_1 (0x1 << 0) 484#define DRIVE_CURRENT_SET_2_LEVEL_0 (0x0 << 0) 485 486/* EXYNOS_DP_LN3_LINK_TRAINING_CTL */ 487#define MAX_PRE_EMPHASIS_REACH_3 (0x1 << 5) 488#define PRE_EMPHASIS_SET_3_SET(x) (((x) & 0x3) << 3) 489#define PRE_EMPHASIS_SET_3_GET(x) (((x) >> 3) & 0x3) 490#define PRE_EMPHASIS_SET_3_MASK (0x3 << 3) 491#define PRE_EMPHASIS_SET_3_SHIFT (3) 492#define PRE_EMPHASIS_SET_3_LEVEL_3 (0x3 << 3) 493#define PRE_EMPHASIS_SET_3_LEVEL_2 (0x2 << 3) 494#define PRE_EMPHASIS_SET_3_LEVEL_1 (0x1 << 3) 495#define PRE_EMPHASIS_SET_3_LEVEL_0 (0x0 << 3) 496#define MAX_DRIVE_CURRENT_REACH_3 (0x1 << 2) 497#define DRIVE_CURRENT_SET_3_MASK (0x3 << 0) 498#define DRIVE_CURRENT_SET_3_SET(x) (((x) & 0x3) << 0) 499#define DRIVE_CURRENT_SET_3_GET(x) (((x) >> 0) & 0x3) 500#define DRIVE_CURRENT_SET_3_LEVEL_3 (0x3 << 0) 501#define DRIVE_CURRENT_SET_3_LEVEL_2 (0x2 << 0) 502#define DRIVE_CURRENT_SET_3_LEVEL_1 (0x1 << 0) 503#define DRIVE_CURRENT_SET_3_LEVEL_0 (0x0 << 0) 504 505/* EXYNOS_DP_VIDEO_CTL_10 */ 506#define FORMAT_SEL (0x1 << 4) 507#define INTERACE_SCAN_CFG (0x1 << 2) 508#define INTERACE_SCAN_CFG_SHIFT (2) 509#define VSYNC_POLARITY_CFG (0x1 << 1) 510#define V_S_POLARITY_CFG_SHIFT (1) 511#define HSYNC_POLARITY_CFG (0x1 << 0) 512#define H_S_POLARITY_CFG_SHIFT (0) 513 514/* EXYNOS_DP_SOC_GENERAL_CTL */ 515#define AUDIO_MODE_SPDIF_MODE (0x1 << 8) 516#define AUDIO_MODE_MASTER_MODE (0x0 << 8) 517#define MASTER_VIDEO_INTERLACE_EN (0x1 << 4) 518#define VIDEO_MASTER_CLK_SEL (0x1 << 2) 519#define VIDEO_MASTER_MODE_EN (0x1 << 1) 520#define VIDEO_MODE_MASK (0x1 << 0) 521#define VIDEO_MODE_SLAVE_MODE (0x1 << 0) 522#define VIDEO_MODE_MASTER_MODE (0x0 << 0) 523 524/* EXYNOS_DP_VIDEO_CTL_1 */ 525#define VIDEO_EN (0x1 << 7) 526#define HDCP_VIDEO_MUTE (0x1 << 6) 527 528/* EXYNOS_DP_VIDEO_CTL_2 */ 529#define IN_D_RANGE_MASK (0x1 << 7) 530#define IN_D_RANGE_SHIFT (7) 531#define IN_D_RANGE_CEA (0x1 << 7) 532#define IN_D_RANGE_VESA (0x0 << 7) 533#define IN_BPC_MASK (0x7 << 4) 534#define IN_BPC_SHIFT (4) 535#define IN_BPC_12_BITS (0x3 << 4) 536#define IN_BPC_10_BITS (0x2 << 4) 537#define IN_BPC_8_BITS (0x1 << 4) 538#define IN_BPC_6_BITS (0x0 << 4) 539#define IN_COLOR_F_MASK (0x3 << 0) 540#define IN_COLOR_F_SHIFT (0) 541#define IN_COLOR_F_YCBCR444 (0x2 << 0) 542#define IN_COLOR_F_YCBCR422 (0x1 << 0) 543#define IN_COLOR_F_RGB (0x0 << 0) 544 545/* EXYNOS_DP_VIDEO_CTL_3 */ 546#define IN_YC_COEFFI_MASK (0x1 << 7) 547#define IN_YC_COEFFI_SHIFT (7) 548#define IN_YC_COEFFI_ITU709 (0x1 << 7) 549#define IN_YC_COEFFI_ITU601 (0x0 << 7) 550#define VID_CHK_UPDATE_TYPE_MASK (0x1 << 4) 551#define VID_CHK_UPDATE_TYPE_SHIFT (4) 552#define VID_CHK_UPDATE_TYPE_1 (0x1 << 4) 553#define VID_CHK_UPDATE_TYPE_0 (0x0 << 4) 554 555/* EXYNOS_DP_TEST_PATTERN_GEN_EN */ 556#define TEST_PATTERN_GEN_EN (0x1 << 0) 557#define TEST_PATTERN_GEN_DIS (0x0 << 0) 558 559/* EXYNOS_DP_TEST_PATTERN_GEN_CTRL */ 560#define TEST_PATTERN_MODE_COLOR_SQUARE (0x3 << 0) 561#define TEST_PATTERN_MODE_BALCK_WHITE_V_LINES (0x2 << 0) 562#define TEST_PATTERN_MODE_COLOR_RAMP (0x1 << 0) 563 564/* EXYNOS_DP_VIDEO_CTL_4 */ 565#define BIST_EN (0x1 << 3) 566#define BIST_WIDTH_MASK (0x1 << 2) 567#define BIST_WIDTH_BAR_32_PIXEL (0x0 << 2) 568#define BIST_WIDTH_BAR_64_PIXEL (0x1 << 2) 569#define BIST_TYPE_MASK (0x3 << 0) 570#define BIST_TYPE_COLOR_BAR (0x0 << 0) 571#define BIST_TYPE_WHITE_GRAY_BLACK_BAR (0x1 << 0) 572#define BIST_TYPE_MOBILE_WHITE_BAR (0x2 << 0) 573 574/* EXYNOS_DP_SYS_CTL_1 */ 575#define DET_STA (0x1 << 2) 576#define FORCE_DET (0x1 << 1) 577#define DET_CTRL (0x1 << 0) 578 579/* EXYNOS_DP_SYS_CTL_2 */ 580#define CHA_CRI(x) (((x) & 0xf) << 4) 581#define CHA_STA (0x1 << 2) 582#define FORCE_CHA (0x1 << 1) 583#define CHA_CTRL (0x1 << 0) 584 585/* EXYNOS_DP_SYS_CTL_3 */ 586#define HPD_STATUS (0x1 << 6) 587#define F_HPD (0x1 << 5) 588#define HPD_CTRL (0x1 << 4) 589#define HDCP_RDY (0x1 << 3) 590#define STRM_VALID (0x1 << 2) 591#define F_VALID (0x1 << 1) 592#define VALID_CTRL (0x1 << 0) 593 594/* EXYNOS_DP_SYS_CTL_4 */ 595#define FIX_M_AUD (0x1 << 4) 596#define ENHANCED (0x1 << 3) 597#define FIX_M_VID (0x1 << 2) 598#define M_VID_UPDATE_CTRL (0x3 << 0) 599 600/* EXYNOS_M_VID_X */ 601#define M_VID0_CFG(x) ((x) & 0xff) 602#define M_VID1_CFG(x) (((x) >> 8) & 0xff) 603#define M_VID2_CFG(x) (((x) >> 16) & 0xff) 604 605/* EXYNOS_M_VID_X */ 606#define N_VID0_CFG(x) ((x) & 0xff) 607#define N_VID1_CFG(x) (((x) >> 8) & 0xff) 608#define N_VID2_CFG(x) (((x) >> 16) & 0xff) 609 610/* DPCD_TRAINING_PATTERN_SET */ 611#define DPCD_SCRAMBLING_DISABLED (0x1 << 5) 612#define DPCD_SCRAMBLING_ENABLED (0x0 << 5) 613#define DPCD_TRAINING_PATTERN_2 (0x2 << 0) 614#define DPCD_TRAINING_PATTERN_1 (0x1 << 0) 615#define DPCD_TRAINING_PATTERN_DISABLED (0x0 << 0) 616 617/* Definition for DPCD Register */ 618#define DPCD_DPCD_REV (0x0000) 619#define DPCD_MAX_LINK_RATE (0x0001) 620#define DPCD_MAX_LANE_COUNT (0x0002) 621#define DPCD_LINK_BW_SET (0x0100) 622#define DPCD_LANE_COUNT_SET (0x0101) 623#define DPCD_TRAINING_PATTERN_SET (0x0102) 624#define DPCD_TRAINING_LANE0_SET (0x0103) 625#define DPCD_LANE0_1_STATUS (0x0202) 626#define DPCD_LN_ALIGN_UPDATED (0x0204) 627#define DPCD_ADJUST_REQUEST_LANE0_1 (0x0206) 628#define DPCD_ADJUST_REQUEST_LANE2_3 (0x0207) 629#define DPCD_TEST_REQUEST (0x0218) 630#define DPCD_TEST_RESPONSE (0x0260) 631#define DPCD_TEST_EDID_CHECKSUM (0x0261) 632#define DPCD_SINK_POWER_STATE (0x0600) 633 634/* DPCD_TEST_REQUEST */ 635#define DPCD_TEST_EDID_READ (0x1 << 2) 636 637/* DPCD_TEST_RESPONSE */ 638#define DPCD_TEST_EDID_CHECKSUM_WRITE (0x1 << 2) 639 640/* DPCD_SINK_POWER_STATE */ 641#define DPCD_SET_POWER_STATE_D0 (0x1 << 0) 642#define DPCD_SET_POWER_STATE_D4 (0x2 << 0) 643 644/* I2C EDID Chip ID, Slave Address */ 645#define I2C_EDID_DEVICE_ADDR (0x50) 646#define I2C_E_EDID_DEVICE_ADDR (0x30) 647#define EDID_BLOCK_LENGTH (0x80) 648#define EDID_HEADER_PATTERN (0x00) 649#define EDID_EXTENSION_FLAG (0x7e) 650#define EDID_CHECKSUM (0x7f) 651 652/* DPCD_LANE0_1_STATUS */ 653#define DPCD_LANE1_SYMBOL_LOCKED (0x1 << 6) 654#define DPCD_LANE1_CHANNEL_EQ_DONE (0x1 << 5) 655#define DPCD_LANE1_CR_DONE (0x1 << 4) 656#define DPCD_LANE0_SYMBOL_LOCKED (0x1 << 2) 657#define DPCD_LANE0_CHANNEL_EQ_DONE (0x1 << 1) 658#define DPCD_LANE0_CR_DONE (0x1 << 0) 659 660/* DPCD_ADJUST_REQUEST_LANE0_1 */ 661#define DPCD_PRE_EMPHASIS_LANE1_MASK (0x3 << 6) 662#define DPCD_PRE_EMPHASIS_LANE1(x) (((x) >> 6) & 0x3) 663#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_3 (0x3 << 6) 664#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_2 (0x2 << 6) 665#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_1 (0x1 << 6) 666#define DPCD_PRE_EMPHASIS_LANE1_LEVEL_0 (0x0 << 6) 667#define DPCD_VOLTAGE_SWING_LANE1_MASK (0x3 << 4) 668#define DPCD_VOLTAGE_SWING_LANE1(x) (((x) >> 4) & 0x3) 669#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_3 (0x3 << 4) 670#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_2 (0x2 << 4) 671#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_1 (0x1 << 4) 672#define DPCD_VOLTAGE_SWING_LANE1_LEVEL_0 (0x0 << 4) 673#define DPCD_PRE_EMPHASIS_LANE0_MASK (0x3 << 2) 674#define DPCD_PRE_EMPHASIS_LANE0(x) (((x) >> 2) & 0x3) 675#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_3 (0x3 << 2) 676#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_2 (0x2 << 2) 677#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_1 (0x1 << 2) 678#define DPCD_PRE_EMPHASIS_LANE0_LEVEL_0 (0x0 << 2) 679#define DPCD_VOLTAGE_SWING_LANE0_MASK (0x3 << 0) 680#define DPCD_VOLTAGE_SWING_LANE0(x) (((x) >> 0) & 0x3) 681#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_3 (0x3 << 0) 682#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_2 (0x2 << 0) 683#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_1 (0x1 << 0) 684#define DPCD_VOLTAGE_SWING_LANE0_LEVEL_0 (0x0 << 0) 685 686/* DPCD_ADJUST_REQUEST_LANE2_3 */ 687#define DPCD_PRE_EMPHASIS_LANE2_MASK (0x3 << 6) 688#define DPCD_PRE_EMPHASIS_LANE2(x) (((x) >> 6) & 0x3) 689#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_3 (0x3 << 6) 690#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_2 (0x2 << 6) 691#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_1 (0x1 << 6) 692#define DPCD_PRE_EMPHASIS_LANE2_LEVEL_0 (0x0 << 6) 693#define DPCD_VOLTAGE_SWING_LANE2_MASK (0x3 << 4) 694#define DPCD_VOLTAGE_SWING_LANE2(x) (((x) >> 4) & 0x3) 695#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_3 (0x3 << 4) 696#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_2 (0x2 << 4) 697#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_1 (0x1 << 4) 698#define DPCD_VOLTAGE_SWING_LANE2_LEVEL_0 (0x0 << 4) 699#define DPCD_PRE_EMPHASIS_LANE3_MASK (0x3 << 2) 700#define DPCD_PRE_EMPHASIS_LANE3(x) (((x) >> 2) & 0x3) 701#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_3 (0x3 << 2) 702#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_2 (0x2 << 2) 703#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_1 (0x1 << 2) 704#define DPCD_PRE_EMPHASIS_LANE3_LEVEL_0 (0x0 << 2) 705#define DPCD_VOLTAGE_SWING_LANE3_MASK (0x3 << 0) 706#define DPCD_VOLTAGE_SWING_LANE3(x) (((x) >> 0) & 0x3) 707#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_3 (0x3 << 0) 708#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_2 (0x2 << 0) 709#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_1 (0x1 << 0) 710#define DPCD_VOLTAGE_SWING_LANE3_LEVEL_0 (0x0 << 0) 711 712/* DPCD_LANE_COUNT_SET */ 713#define DPCD_ENHANCED_FRAME_EN (0x1 << 7) 714#define DPCD_LN_COUNT_SET(x) ((x) & 0x1f) 715 716/* DPCD_LANE_ALIGN__STATUS_UPDATED */ 717#define DPCD_LINK_STATUS_UPDATED (0x1 << 7) 718#define DPCD_DOWNSTREAM_PORT_STATUS_CHANGED (0x1 << 6) 719#define DPCD_INTERLANE_ALIGN_DONE (0x1 << 0) 720 721/* DPCD_TRAINING_LANE0_SET */ 722#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_3 (0x3 << 3) 723#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_2 (0x2 << 3) 724#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_1 (0x1 << 3) 725#define DPCD_PRE_EMPHASIS_SET_PATTERN_2_LEVEL_0 (0x0 << 3) 726#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_3 (0x3 << 0) 727#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_2 (0x2 << 0) 728#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_1 (0x1 << 0) 729#define DPCD_VOLTAGE_SWING_SET_PATTERN_1_LEVEL_0 (0x0 << 0) 730 731#define DPCD_REQ_ADJ_SWING (0x00) 732#define DPCD_REQ_ADJ_EMPHASIS (0x01) 733 734#define DP_LANE_STAT_CR_DONE (0x01 << 0) 735#define DP_LANE_STAT_CE_DONE (0x01 << 1) 736#define DP_LANE_STAT_SYM_LOCK (0x01 << 2) 737 738#endif 739