LXR uboot/arch/powerpc/cpu/mpc5xx/cpu

   1/*
   2 * (C) Copyright 2003  Martin Winistoerfer, martinwinistoerfer@gmx.ch.
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7/*
   8 * File:                cpu_init.c
   9 *
  10 * Discription:         Contains initialisation functions to setup
  11 *                      the cpu properly
  12 *
  13 */
  14
  15#include <common.h>
  16#include <mpc5xx.h>
  17#include <watchdog.h>
  18
  19/*
  20 * Setup essential cpu registers to run
  21 */
  22void cpu_init_f (volatile immap_t * immr)
  23{
  24        volatile memctl5xx_t *memctl = &immr->im_memctl;
  25        ulong reg;
  26
  27        /* SYPCR - contains watchdog control. This will enable watchdog */
  28        /* if CONFIG_WATCHDOG is set */
  29        immr->im_siu_conf.sc_sypcr = CONFIG_SYS_SYPCR;
  30
  31#if defined(CONFIG_WATCHDOG)
  32        reset_5xx_watchdog (immr);
  33#endif
  34
  35        /* SIUMCR - contains debug pin configuration */
  36        immr->im_siu_conf.sc_siumcr |= CONFIG_SYS_SIUMCR;
  37
  38        /* Initialize timebase. Unlock TBSCRK */
  39        immr->im_sitk.sitk_tbscrk = KAPWR_KEY;
  40        immr->im_sit.sit_tbscr = CONFIG_SYS_TBSCR;
  41
  42        /* Full IMB bus speed */
  43        immr->im_uimb.uimb_umcr = CONFIG_SYS_UMCR;
  44
  45        /* Time base and decrementer will be enables (TBE) */
  46        /* in init_timebase() in time.c called from board_init_f(). */
  47
  48        /* Initialize the PIT. Unlock PISCRK */
  49        immr->im_sitk.sitk_piscrk = KAPWR_KEY;
  50        immr->im_sit.sit_piscr = CONFIG_SYS_PISCR;
  51
  52#if !defined(CONFIG_PATI)
  53        /* PATI sest PLL in start.S */
  54        /* PLL (CPU clock) settings */
  55        immr->im_clkrstk.cark_plprcrk = KAPWR_KEY;
  56
  57        /* If CONFIG_SYS_PLPRCR (set in the various *_config.h files) tries to
  58         * set the MF field, then just copy CONFIG_SYS_PLPRCR over car_plprcr,
  59         * otherwise OR in CONFIG_SYS_PLPRCR so we do not change the currentMF
  60         * field value.
  61         */
  62#if ((CONFIG_SYS_PLPRCR & PLPRCR_MF_MSK) != 0)
  63        reg = CONFIG_SYS_PLPRCR;                        /* reset control bits   */
  64#else
  65        reg = immr->im_clkrst.car_plprcr;
  66        reg &= PLPRCR_MF_MSK;                   /* isolate MF field */
  67        reg |= CONFIG_SYS_PLPRCR;                       /* reset control bits   */
  68#endif
  69        immr->im_clkrst.car_plprcr = reg;
  70
  71#endif /* !defined(CONFIG_PATI) */
  72
  73        /* System integration timers. CONFIG_SYS_MASK has EBDF configuration */
  74        immr->im_clkrstk.cark_sccrk = KAPWR_KEY;
  75        reg = immr->im_clkrst.car_sccr;
  76        reg &= SCCR_MASK;
  77        reg |= CONFIG_SYS_SCCR;
  78        immr->im_clkrst.car_sccr = reg;
  79
  80        /* Memory Controller */
  81        memctl->memc_br0 = CONFIG_SYS_BR0_PRELIM;
  82        memctl->memc_or0 = CONFIG_SYS_OR0_PRELIM;
  83
  84#if (defined(CONFIG_SYS_OR1_PRELIM) && defined(CONFIG_SYS_BR1_PRELIM))
  85        memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
  86        memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
  87#endif
  88
  89#if defined(CONFIG_SYS_OR2_PRELIM) && defined(CONFIG_SYS_BR2_PRELIM)
  90        memctl->memc_or2 = CONFIG_SYS_OR2_PRELIM;
  91        memctl->memc_br2 = CONFIG_SYS_BR2_PRELIM;
  92#endif
  93
  94#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM)
  95        memctl->memc_or3 = CONFIG_SYS_OR3_PRELIM;
  96        memctl->memc_br3 = CONFIG_SYS_BR3_PRELIM;
  97#endif
  98
  99}
 100
 101/*
 102 * Initialize higher level parts of cpu
 103 */
 104int cpu_init_r (void)
 105{
 106        /* Nothing to do at the moment */
 107        return (0);
 108}
 109