uboot/board/comelit/dig297/dig297.h
<<
>>
Prefs 
   1/*
   2 * (C) Copyright 2011 Comelit Group SpA
   3 * Luca Ceresoli <luca.ceresoli@comelit.it>
   4 *
   5 * Based on board/ti/beagle/beagle.h:
   6 * (C) Copyright 2008
   7 * Dirk Behme <dirk.behme@gmail.com>
   8 *
   9 * SPDX-License-Identifier:     GPL-2.0+
  10 */
  11#ifndef _DIG297_H_
  12#define _DIG297_H_
  13
  14const omap3_sysinfo sysinfo = {
  15        DDR_STACKED,
  16        "OMAP3 DIG297 board",
  17        "NAND",
  18};
  19
  20/*
  21 * IEN  - Input Enable
  22 * IDIS - Input Disable
  23 * PTD  - Pull type Down
  24 * PTU  - Pull type Up
  25 * DIS  - Pull type selection is inactive
  26 * EN   - Pull type selection is active
  27 * M0   - Mode 0
  28 * The commented string gives the final mux configuration for that pin
  29 */
  30#define MUX_DIG297() \
  31/*SDRC*/\
  32        MUX_VAL(CP(SDRC_D0),        (IEN  | PTD | DIS | M0)) /*SDRC_D0*/\
  33        MUX_VAL(CP(SDRC_D1),        (IEN  | PTD | DIS | M0)) /*SDRC_D1*/\
  34        MUX_VAL(CP(SDRC_D2),        (IEN  | PTD | DIS | M0)) /*SDRC_D2*/\
  35        MUX_VAL(CP(SDRC_D3),        (IEN  | PTD | DIS | M0)) /*SDRC_D3*/\
  36        MUX_VAL(CP(SDRC_D4),        (IEN  | PTD | DIS | M0)) /*SDRC_D4*/\
  37        MUX_VAL(CP(SDRC_D5),        (IEN  | PTD | DIS | M0)) /*SDRC_D5*/\
  38        MUX_VAL(CP(SDRC_D6),        (IEN  | PTD | DIS | M0)) /*SDRC_D6*/\
  39        MUX_VAL(CP(SDRC_D7),        (IEN  | PTD | DIS | M0)) /*SDRC_D7*/\
  40        MUX_VAL(CP(SDRC_D8),        (IEN  | PTD | DIS | M0)) /*SDRC_D8*/\
  41        MUX_VAL(CP(SDRC_D9),        (IEN  | PTD | DIS | M0)) /*SDRC_D9*/\
  42        MUX_VAL(CP(SDRC_D10),       (IEN  | PTD | DIS | M0)) /*SDRC_D10*/\
  43        MUX_VAL(CP(SDRC_D11),       (IEN  | PTD | DIS | M0)) /*SDRC_D11*/\
  44        MUX_VAL(CP(SDRC_D12),       (IEN  | PTD | DIS | M0)) /*SDRC_D12*/\
  45        MUX_VAL(CP(SDRC_D13),       (IEN  | PTD | DIS | M0)) /*SDRC_D13*/\
  46        MUX_VAL(CP(SDRC_D14),       (IEN  | PTD | DIS | M0)) /*SDRC_D14*/\
  47        MUX_VAL(CP(SDRC_D15),       (IEN  | PTD | DIS | M0)) /*SDRC_D15*/\
  48        MUX_VAL(CP(SDRC_D16),       (IEN  | PTD | DIS | M0)) /*SDRC_D16*/\
  49        MUX_VAL(CP(SDRC_D17),       (IEN  | PTD | DIS | M0)) /*SDRC_D17*/\
  50        MUX_VAL(CP(SDRC_D18),       (IEN  | PTD | DIS | M0)) /*SDRC_D18*/\
  51        MUX_VAL(CP(SDRC_D19),       (IEN  | PTD | DIS | M0)) /*SDRC_D19*/\
  52        MUX_VAL(CP(SDRC_D20),       (IEN  | PTD | DIS | M0)) /*SDRC_D20*/\
  53        MUX_VAL(CP(SDRC_D21),       (IEN  | PTD | DIS | M0)) /*SDRC_D21*/\
  54        MUX_VAL(CP(SDRC_D22),       (IEN  | PTD | DIS | M0)) /*SDRC_D22*/\
  55        MUX_VAL(CP(SDRC_D23),       (IEN  | PTD | DIS | M0)) /*SDRC_D23*/\
  56        MUX_VAL(CP(SDRC_D24),       (IEN  | PTD | DIS | M0)) /*SDRC_D24*/\
  57        MUX_VAL(CP(SDRC_D25),       (IEN  | PTD | DIS | M0)) /*SDRC_D25*/\
  58        MUX_VAL(CP(SDRC_D26),       (IEN  | PTD | DIS | M0)) /*SDRC_D26*/\
  59        MUX_VAL(CP(SDRC_D27),       (IEN  | PTD | DIS | M0)) /*SDRC_D27*/\
  60        MUX_VAL(CP(SDRC_D28),       (IEN  | PTD | DIS | M0)) /*SDRC_D28*/\
  61        MUX_VAL(CP(SDRC_D29),       (IEN  | PTD | DIS | M0)) /*SDRC_D29*/\
  62        MUX_VAL(CP(SDRC_D30),       (IEN  | PTD | DIS | M0)) /*SDRC_D30*/\
  63        MUX_VAL(CP(SDRC_D31),       (IEN  | PTD | DIS | M0)) /*SDRC_D31*/\
  64        MUX_VAL(CP(SDRC_CLK),       (IEN  | PTD | DIS | M0)) /*SDRC_CLK*/\
  65        MUX_VAL(CP(SDRC_DQS0),      (IEN  | PTD | DIS | M0)) /*SDRC_DQS0*/\
  66        MUX_VAL(CP(SDRC_DQS1),      (IEN  | PTD | DIS | M0)) /*SDRC_DQS1*/\
  67        MUX_VAL(CP(SDRC_DQS2),      (IEN  | PTD | DIS | M0)) /*SDRC_DQS2*/\
  68        MUX_VAL(CP(SDRC_DQS3),      (IEN  | PTD | DIS | M0)) /*SDRC_DQS3*/\
  69        MUX_VAL(CP(SDRC_CKE0),      (IDIS | PTU | EN  | M0)) /*sdrc_cke0*/\
  70        MUX_VAL(CP(SDRC_CKE1),      (IDIS | PTU | DIS | M0)) /*sdrc_cke1: NC*/\
  71/*GPMC*/\
  72        MUX_VAL(CP(GPMC_A1),        (IDIS | PTU | EN  | M0)) /*GPMC_A1*/\
  73        MUX_VAL(CP(GPMC_A2),        (IDIS | PTU | EN  | M0)) /*GPMC_A2*/\
  74        MUX_VAL(CP(GPMC_A3),        (IDIS | PTU | EN  | M0)) /*GPMC_A3*/\
  75        MUX_VAL(CP(GPMC_A4),        (IDIS | PTU | EN  | M0)) /*GPMC_A4*/\
  76        MUX_VAL(CP(GPMC_A5),        (IDIS | PTU | EN  | M0)) /*GPMC_A5*/\
  77        MUX_VAL(CP(GPMC_A6),        (IDIS | PTU | EN  | M0)) /*GPMC_A6*/\
  78        MUX_VAL(CP(GPMC_A7),        (IDIS | PTU | EN  | M0)) /*GPMC_A7*/\
  79        MUX_VAL(CP(GPMC_A8),        (IDIS | PTU | EN  | M0)) /*GPMC_A8*/\
  80        MUX_VAL(CP(GPMC_A9),        (IDIS | PTU | EN  | M0)) /*GPMC_A9*/\
  81        MUX_VAL(CP(GPMC_A10),       (IDIS | PTU | EN  | M0)) /*GPMC_A10*/\
  82        MUX_VAL(CP(GPMC_D0),        (IEN  | PTU | EN  | M0)) /*GPMC_D0*/\
  83        MUX_VAL(CP(GPMC_D1),        (IEN  | PTU | EN  | M0)) /*GPMC_D1*/\
  84        MUX_VAL(CP(GPMC_D2),        (IEN  | PTU | EN  | M0)) /*GPMC_D2*/\
  85        MUX_VAL(CP(GPMC_D3),        (IEN  | PTU | EN  | M0)) /*GPMC_D3*/\
  86        MUX_VAL(CP(GPMC_D4),        (IEN  | PTU | EN  | M0)) /*GPMC_D4*/\
  87        MUX_VAL(CP(GPMC_D5),        (IEN  | PTU | EN  | M0)) /*GPMC_D5*/\
  88        MUX_VAL(CP(GPMC_D6),        (IEN  | PTU | EN  | M0)) /*GPMC_D6*/\
  89        MUX_VAL(CP(GPMC_D7),        (IEN  | PTU | EN  | M0)) /*GPMC_D7*/\
  90        MUX_VAL(CP(GPMC_D8),        (IEN  | PTU | EN  | M0)) /*GPMC_D8*/\
  91        MUX_VAL(CP(GPMC_D9),        (IEN  | PTU | EN  | M0)) /*GPMC_D9*/\
  92        MUX_VAL(CP(GPMC_D10),       (IEN  | PTU | EN  | M0)) /*GPMC_D10*/\
  93        MUX_VAL(CP(GPMC_D11),       (IEN  | PTU | EN  | M0)) /*GPMC_D11*/\
  94        MUX_VAL(CP(GPMC_D12),       (IEN  | PTU | EN  | M0)) /*GPMC_D12*/\
  95        MUX_VAL(CP(GPMC_D13),       (IEN  | PTU | EN  | M0)) /*GPMC_D13*/\
  96        MUX_VAL(CP(GPMC_D14),       (IEN  | PTU | EN  | M0)) /*GPMC_D14*/\
  97        MUX_VAL(CP(GPMC_D15),       (IEN  | PTU | EN  | M0)) /*GPMC_D15*/\
  98        MUX_VAL(CP(GPMC_NCS0),      (IDIS | PTU | EN  | M0)) /*NAND*/\
  99        /* GPMC_nCS1/2: not available on CUS package*/\
 100        MUX_VAL(CP(GPMC_NCS3),      (IDIS | PTU | DIS | M0)) /*GPMC_nCS3*/\
 101        MUX_VAL(CP(GPMC_NCS4),      (IDIS | PTU | DIS | M0)) /*GPMC_nCS4*/\
 102        MUX_VAL(CP(GPMC_NCS5),      (IDIS | PTU | EN  | M0)) /*GPMC_nCS5*/\
 103        MUX_VAL(CP(GPMC_NCS6),      (IEN  | PTD | DIS | M1)) /*SYS_nDMA_REQ2*/\
 104        MUX_VAL(CP(GPMC_NCS7),      (IEN  | PTU | EN  | M1)) /*SYS_nDMA_REQ3*/\
 105        MUX_VAL(CP(GPMC_NBE1),      (IDIS | PTD | DIS | M0)) /*GPMC_nBE1: NC*/\
 106        /* GPMC_WAIT2: not available on CUS package*/\
 107        MUX_VAL(CP(GPMC_WAIT3),     (IDIS | PTU | DIS | M0)) /*GPMC_WAIT3: NC*/\
 108        /* GPMC_CLK: NC (only asyncronous peripherals are connected) */\
 109        MUX_VAL(CP(GPMC_CLK),       (IDIS | PTD | DIS | M0)) \
 110        MUX_VAL(CP(GPMC_NADV_ALE),  (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\
 111        MUX_VAL(CP(GPMC_NOE),       (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\
 112        MUX_VAL(CP(GPMC_NWE),       (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\
 113        MUX_VAL(CP(GPMC_NBE0_CLE),  (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\
 114        MUX_VAL(CP(GPMC_NWP),       (IEN  | PTD | DIS | M0)) /*GPMC_nWP*/\
 115        MUX_VAL(CP(GPMC_WAIT0),     (IEN  | PTU | EN  | M0)) /*GPMC_WAIT0*/\
 116        /* GPMC_WAIT1: not available on CUS package*/\
 117/*DSS*/\
 118        MUX_VAL(CP(DSS_PCLK),       (IDIS | PTD | DIS | M0)) /*DSS_PCLK*/\
 119        MUX_VAL(CP(DSS_HSYNC),      (IDIS | PTD | DIS | M0)) /*DSS_HSYNC*/\
 120        MUX_VAL(CP(DSS_VSYNC),      (IDIS | PTD | DIS | M0)) /*DSS_VSYNC*/\
 121        /* DSS_ACBIAS: AC BIAS: connected to TFT, not to be driven */\
 122        MUX_VAL(CP(DSS_ACBIAS),     (IDIS | PTU | EN  | M7))\
 123        MUX_VAL(CP(DSS_DATA0),      (IDIS | PTD | DIS | M0)) /*DSS_DATA0*/\
 124        MUX_VAL(CP(DSS_DATA1),      (IDIS | PTD | DIS | M0)) /*DSS_DATA1*/\
 125        MUX_VAL(CP(DSS_DATA2),      (IDIS | PTD | DIS | M0)) /*DSS_DATA2*/\
 126        MUX_VAL(CP(DSS_DATA3),      (IDIS | PTD | DIS | M0)) /*DSS_DATA3*/\
 127        MUX_VAL(CP(DSS_DATA4),      (IDIS | PTD | DIS | M0)) /*DSS_DATA4*/\
 128        MUX_VAL(CP(DSS_DATA5),      (IDIS | PTD | DIS | M0)) /*DSS_DATA5*/\
 129        MUX_VAL(CP(DSS_DATA6),      (IDIS | PTD | DIS | M0)) /*DSS_DATA6*/\
 130        MUX_VAL(CP(DSS_DATA7),      (IDIS | PTD | DIS | M0)) /*DSS_DATA7*/\
 131        MUX_VAL(CP(DSS_DATA8),      (IDIS | PTD | DIS | M0)) /*DSS_DATA8*/\
 132        MUX_VAL(CP(DSS_DATA9),      (IDIS | PTD | DIS | M0)) /*DSS_DATA9*/\
 133        MUX_VAL(CP(DSS_DATA10),     (IDIS | PTD | DIS | M0)) /*DSS_DATA10*/\
 134        MUX_VAL(CP(DSS_DATA11),     (IDIS | PTD | DIS | M0)) /*DSS_DATA11*/\
 135        MUX_VAL(CP(DSS_DATA12),     (IDIS | PTD | DIS | M0)) /*DSS_DATA12*/\
 136        MUX_VAL(CP(DSS_DATA13),     (IDIS | PTD | DIS | M0)) /*DSS_DATA13*/\
 137        MUX_VAL(CP(DSS_DATA14),     (IDIS | PTD | DIS | M0)) /*DSS_DATA14*/\
 138        MUX_VAL(CP(DSS_DATA15),     (IDIS | PTD | DIS | M0)) /*DSS_DATA15*/\
 139        MUX_VAL(CP(DSS_DATA16),     (IDIS | PTD | DIS | M0)) /*DSS_DATA16*/\
 140        MUX_VAL(CP(DSS_DATA17),     (IDIS | PTD | DIS | M0)) /*DSS_DATA17*/\
 141        MUX_VAL(CP(DSS_DATA18),     (IDIS | PTD | DIS | M0)) /*DSS_DATA18*/\
 142        MUX_VAL(CP(DSS_DATA19),     (IDIS | PTD | DIS | M0)) /*DSS_DATA19*/\
 143        MUX_VAL(CP(DSS_DATA20),     (IDIS | PTD | DIS | M0)) /*DSS_DATA20*/\
 144        MUX_VAL(CP(DSS_DATA21),     (IDIS | PTD | DIS | M0)) /*DSS_DATA21*/\
 145        MUX_VAL(CP(DSS_DATA22),     (IDIS | PTD | DIS | M0)) /*DSS_DATA22*/\
 146        MUX_VAL(CP(DSS_DATA23),     (IDIS | PTD | DIS | M0)) /*DSS_DATA23*/\
 147/*CAMERA*/\
 148        MUX_VAL(CP(CAM_HS),         (IEN  | PTU | EN  | M0)) /*CAM_HS */\
 149        MUX_VAL(CP(CAM_VS),         (IEN  | PTU | EN  | M0)) /*CAM_VS */\
 150        MUX_VAL(CP(CAM_XCLKA),      (IDIS | PTD | DIS | M0)) /*CAM_XCLKA*/\
 151        MUX_VAL(CP(CAM_PCLK),       (IEN  | PTU | EN  | M0)) /*CAM_PCLK*/\
 152        MUX_VAL(CP(CAM_FLD),        (IDIS | PTD | DIS | M4)) /*GPIO_98*/\
 153        MUX_VAL(CP(CAM_D0),         (IEN  | PTD | DIS | M0)) /*CAM_D0*/\
 154        MUX_VAL(CP(CAM_D1),         (IEN  | PTD | DIS | M0)) /*CAM_D1*/\
 155        MUX_VAL(CP(CAM_D2),         (IEN  | PTD | DIS | M0)) /*CAM_D2*/\
 156        MUX_VAL(CP(CAM_D3),         (IEN  | PTD | DIS | M0)) /*CAM_D3*/\
 157        MUX_VAL(CP(CAM_D4),         (IEN  | PTD | DIS | M0)) /*CAM_D4*/\
 158        MUX_VAL(CP(CAM_D5),         (IEN  | PTD | DIS | M0)) /*CAM_D5*/\
 159        MUX_VAL(CP(CAM_D6),         (IEN  | PTD | DIS | M0)) /*CAM_D6*/\
 160        MUX_VAL(CP(CAM_D7),         (IEN  | PTD | DIS | M0)) /*CAM_D7*/\
 161        MUX_VAL(CP(CAM_D8),         (IEN  | PTD | DIS | M0)) /*CAM_D8*/\
 162        MUX_VAL(CP(CAM_D9),         (IEN  | PTD | DIS | M0)) /*CAM_D9*/\
 163        MUX_VAL(CP(CAM_D10),        (IEN  | PTD | DIS | M0)) /*CAM_D10*/\
 164        MUX_VAL(CP(CAM_D11),        (IEN  | PTD | DIS | M0)) /*CAM_D11*/\
 165        MUX_VAL(CP(CAM_XCLKB),      (IDIS | PTD | DIS | M0)) /*CAM_XCLKB*/\
 166        MUX_VAL(CP(CAM_WEN),        (IEN  | PTD | DIS | M4)) /*GPIO_167*/\
 167        MUX_VAL(CP(CAM_STROBE),     (IDIS | PTD | DIS | M0)) /*CAM_STROBE*/\
 168        MUX_VAL(CP(CSI2_DX0),       (IEN  | PTD | DIS | M0)) /*CSI2_DX0*/\
 169        MUX_VAL(CP(CSI2_DY0),       (IEN  | PTD | DIS | M0)) /*CSI2_DY0*/\
 170        MUX_VAL(CP(CSI2_DX1),       (IEN  | PTD | DIS | M0)) /*CSI2_DX1*/\
 171        MUX_VAL(CP(CSI2_DY1),       (IEN  | PTD | DIS | M0)) /*CSI2_DY1*/\
 172/*Audio Interface */\
 173        MUX_VAL(CP(MCBSP2_FSX),     (IEN  | PTD | DIS | M0)) /*McBSP2_FSX*/\
 174        MUX_VAL(CP(MCBSP2_CLKX),    (IEN  | PTD | DIS | M0)) /*McBSP2_CLKX*/\
 175        MUX_VAL(CP(MCBSP2_DR),      (IEN  | PTD | DIS | M0)) /*McBSP2_DR*/\
 176        MUX_VAL(CP(MCBSP2_DX),      (IDIS | PTD | DIS | M0)) /*McBSP2_DX*/\
 177/*Expansion card */\
 178        MUX_VAL(CP(MMC1_CLK),       (IDIS | PTU | EN  | M0)) /*MMC1_CLK*/\
 179        MUX_VAL(CP(MMC1_CMD),       (IEN  | PTU | EN  | M0)) /*MMC1_CMD*/\
 180        MUX_VAL(CP(MMC1_DAT0),      (IEN  | PTU | EN  | M0)) /*MMC1_DAT0*/\
 181        MUX_VAL(CP(MMC1_DAT1),      (IEN  | PTU | EN  | M0)) /*MMC1_DAT1*/\
 182        MUX_VAL(CP(MMC1_DAT2),      (IEN  | PTU | EN  | M0)) /*MMC1_DAT2*/\
 183        MUX_VAL(CP(MMC1_DAT3),      (IEN  | PTU | EN  | M0)) /*MMC1_DAT3*/\
 184        MUX_VAL(CP(MMC1_DAT4),      (IEN  | PTU | EN  | M0)) /*MMC1_DAT4*/\
 185        MUX_VAL(CP(MMC1_DAT5),      (IEN  | PTU | EN  | M0)) /*MMC1_DAT5*/\
 186        MUX_VAL(CP(MMC1_DAT6),      (IEN  | PTU | EN  | M0)) /*MMC1_DAT6*/\
 187        MUX_VAL(CP(MMC1_DAT7),      (IEN  | PTU | EN  | M0)) /*MMC1_DAT7*/\
 188/*Wireless LAN */\
 189        MUX_VAL(CP(MMC2_CLK),       (IEN  | PTU | EN  | M4)) /*GPIO_130*/\
 190        MUX_VAL(CP(MMC2_CMD),       (IEN  | PTU | EN  | M4)) /*GPIO_131*/\
 191        MUX_VAL(CP(MMC2_DAT0),      (IEN  | PTU | EN  | M4)) /*GPIO_132*/\
 192        MUX_VAL(CP(MMC2_DAT1),      (IEN  | PTU | EN  | M4)) /*GPIO_133*/\
 193        MUX_VAL(CP(MMC2_DAT2),      (IEN  | PTU | EN  | M4)) /*GPIO_134*/\
 194        MUX_VAL(CP(MMC2_DAT3),      (IEN  | PTU | EN  | M4)) /*GPIO_135*/\
 195        MUX_VAL(CP(MMC2_DAT4),      (IEN  | PTU | EN  | M4)) /*GPIO_136*/\
 196        MUX_VAL(CP(MMC2_DAT5),      (IEN  | PTU | EN  | M4)) /*GPIO_137*/\
 197        MUX_VAL(CP(MMC2_DAT6),      (IEN  | PTU | EN  | M4)) /*GPIO_138*/\
 198        MUX_VAL(CP(MMC2_DAT7),      (IEN  | PTU | EN  | M4)) /*GPIO_139*/\
 199/*Bluetooth*/\
 200        MUX_VAL(CP(MCBSP3_DX),      (IEN  | PTD | DIS | M1)) /*UART2_CTS*/\
 201        MUX_VAL(CP(MCBSP3_DR),      (IDIS | PTD | DIS | M1)) /*UART2_RTS*/\
 202        MUX_VAL(CP(MCBSP3_CLKX),    (IDIS | PTD | DIS | M1)) /*UART2_TX*/\
 203        MUX_VAL(CP(MCBSP3_FSX),     (IEN  | PTD | DIS | M1)) /*UART2_RX*/\
 204        MUX_VAL(CP(UART2_CTS),      (IEN  | PTD | DIS | M4)) /*GPIO_144*/\
 205        MUX_VAL(CP(UART2_RTS),      (IEN  | PTD | DIS | M4)) /*GPIO_145*/\
 206        MUX_VAL(CP(UART2_TX),       (IEN  | PTD | DIS | M4)) /*GPIO_146*/\
 207        MUX_VAL(CP(UART2_RX),       (IEN  | PTD | DIS | M4)) /*GPIO_147*/\
 208/*Modem Interface */\
 209        MUX_VAL(CP(UART1_TX),       (IDIS | PTD | DIS | M0)) /*UART1_TX*/\
 210        MUX_VAL(CP(UART1_RTS),      (IDIS | PTD | DIS | M4)) /*GPIO_149*/ \
 211        MUX_VAL(CP(UART1_CTS),      (IDIS | PTD | DIS | M4)) /*GPIO_150*/ \
 212        MUX_VAL(CP(UART1_RX),       (IEN  | PTD | DIS | M0)) /*UART1_RX*/\
 213        MUX_VAL(CP(MCBSP4_CLKX),    (IEN  | PTD | DIS | M1)) /*SSI1_DAT_RX*/\
 214        MUX_VAL(CP(MCBSP4_DR),      (IEN  | PTD | DIS | M1)) /*SSI1_FLAG_RX*/\
 215        MUX_VAL(CP(MCBSP4_DX),      (IEN  | PTD | DIS | M1)) /*SSI1_RDY_RX*/\
 216        MUX_VAL(CP(MCBSP4_FSX),     (IEN  | PTD | DIS | M1)) /*SSI1_WAKE*/\
 217        MUX_VAL(CP(MCBSP_CLKS),     (IEN  | PTU | DIS | M0)) /*McBSP_CLKS*/\
 218/*Serial Interface*/\
 219        MUX_VAL(CP(UART3_CTS_RCTX), (IEN  | PTD | EN  | M0)) /*UART3_CTS_RCTX*/\
 220        MUX_VAL(CP(UART3_RX_IRRX),  (IEN  | PTD | DIS | M0)) /*UART3_RX_IRRX*/\
 221        MUX_VAL(CP(UART3_TX_IRTX),  (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\
 222        MUX_VAL(CP(HSUSB0_CLK),     (IEN  | PTD | DIS | M0)) /*HSUSB0_CLK*/\
 223        MUX_VAL(CP(HSUSB0_STP),     (IDIS | PTU | EN  | M0)) /*HSUSB0_STP*/\
 224        MUX_VAL(CP(HSUSB0_DIR),     (IEN  | PTD | DIS | M0)) /*HSUSB0_DIR*/\
 225        MUX_VAL(CP(HSUSB0_NXT),     (IEN  | PTD | DIS | M0)) /*HSUSB0_NXT*/\
 226        MUX_VAL(CP(HSUSB0_DATA0),   (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA0*/\
 227        MUX_VAL(CP(HSUSB0_DATA1),   (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA1*/\
 228        MUX_VAL(CP(HSUSB0_DATA2),   (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA2*/\
 229        MUX_VAL(CP(HSUSB0_DATA3),   (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA3*/\
 230        MUX_VAL(CP(HSUSB0_DATA4),   (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA4*/\
 231        MUX_VAL(CP(HSUSB0_DATA5),   (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA5*/\
 232        MUX_VAL(CP(HSUSB0_DATA6),   (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA6*/\
 233        MUX_VAL(CP(HSUSB0_DATA7),   (IEN  | PTD | DIS | M0)) /*HSUSB0_DATA7*/\
 234        MUX_VAL(CP(I2C1_SCL),       (IEN  | PTU | EN  | M0)) /*I2C1_SCL*/\
 235        MUX_VAL(CP(I2C1_SDA),       (IEN  | PTU | EN  | M0)) /*I2C1_SDA*/\
 236        MUX_VAL(CP(I2C2_SCL),       (IEN  | PTU | EN  | M4)) /*GPIO_168*/\
 237        MUX_VAL(CP(I2C2_SDA),       (IEN  | PTU | EN  | M4)) /*GPIO_183*/\
 238        MUX_VAL(CP(I2C3_SCL),       (IEN  | PTU | EN  | M0)) /*I2C3_SCL*/\
 239        MUX_VAL(CP(I2C3_SDA),       (IEN  | PTU | EN  | M0)) /*I2C3_SDA*/\
 240        MUX_VAL(CP(I2C4_SCL),       (IEN  | PTU | EN  | M0)) /*I2C4_SCL*/\
 241        MUX_VAL(CP(I2C4_SDA),       (IEN  | PTU | EN  | M0)) /*I2C4_SDA*/\
 242/* USB EHCI (port 2) */\
 243        MUX_VAL(CP(ETK_D14_ES2),    (IEN  | PTU | DIS | M3)) /*HSUSB2_DATA0*/\
 244        MUX_VAL(CP(ETK_D15_ES2),    (IEN  | PTU | DIS | M3)) /*HSUSB2_DATA1*/\
 245/* MCSPI1: to TOUCH controller TSC2046 (ADS7846 compatible).*/\
 246        /*
 247         * McSPI1_CLK.
 248         * IEN needed fot the McSPI to "receive" the clock and be able to
 249         * sample SOMI. See http://e2e.ti.com/support/arm174_microprocessors/
 250         * omap_applications_processors/f/42/p/29444/102394.aspx#102394
 251         */\
 252        MUX_VAL(CP(MCSPI1_CLK),     (IEN  | PTD | EN  | M0))\
 253        MUX_VAL(CP(MCSPI1_SIMO),    (IDIS | PTD | EN  | M0)) /*McSPI1_SIMO*/\
 254        MUX_VAL(CP(MCSPI1_SOMI),    (IEN  | PTD | EN  | M0)) /*McSPI1_SOMI*/\
 255        MUX_VAL(CP(MCSPI1_CS0),     (IDIS | PTU | EN  | M0)) /*McSPI1_CS0*/\
 256/* MCSPI2: to HIMAX TFT controller.*/\
 257        MUX_VAL(CP(MCSPI2_CLK),     (IDIS | PTD | EN  | M0)) /*MCSPI2_CLK*/\
 258        MUX_VAL(CP(MCSPI2_SIMO),    (IDIS | PTD | EN  | M0)) /*MCSPI3_SIMO*/\
 259        /* MCSPI3_SOMI: NC because HIMAX in monodirectional (no SOMI line) */\
 260        MUX_VAL(CP(MCSPI2_SOMI),    (IDIS | PTU | DIS | M7))\
 261        MUX_VAL(CP(MCSPI2_CS0),     (IDIS | PTU | EN  | M0)) /*MCSPI3_CS0*/\
 262        MUX_VAL(CP(MCSPI2_CS1),     (IDIS | PTU | DIS | M7)) /*Safe mode: NC*/\
 263/* GPIO */\
 264        MUX_VAL(CP(SYS_BOOT5),      (IEN  | PTD | DIS | M4)) /*GPIO_7*/\
 265        MUX_VAL(CP(ETK_CLK_ES2),    (IDIS | PTU | EN  | M4)) /*GPIO_12*/\
 266        MUX_VAL(CP(ETK_CTL_ES2),    (IEN  | PTU | EN  | M4)) /*GPIO_13*/\
 267        MUX_VAL(CP(ETK_D0_ES2),     (IEN  | PTU | DIS | M4)) /*GPIO_14*/\
 268        MUX_VAL(CP(ETK_D1_ES2),     (IDIS | PTD | EN  | M4)) /*GPIO_15*/\
 269        MUX_VAL(CP(ETK_D2_ES2),     (IDIS | PTD | EN  | M4)) /*GPIO_16*/\
 270        MUX_VAL(CP(ETK_D3_ES2),     (IEN  | PTU | DIS | M4)) /*GPIO_17*/\
 271        MUX_VAL(CP(ETK_D4_ES2),     (IDIS | PTD | EN  | M4)) /*GPIO_18*/\
 272        MUX_VAL(CP(ETK_D5_ES2),     (IDIS | PTD | EN  | M4)) /*GPIO_19*/\
 273        MUX_VAL(CP(ETK_D6_ES2),     (IDIS | PTD | EN  | M4)) /*GPIO_20*/\
 274        MUX_VAL(CP(ETK_D7_ES2),     (IDIS | PTD | EN  | M4)) /*GPIO_21*/\
 275        MUX_VAL(CP(ETK_D9_ES2),     (IEN  | PTU | DIS | M4)) /*GPIO_23*/\
 276        MUX_VAL(CP(ETK_D10_ES2),    (IDIS | PTD | EN  | M4)) /*GPIO_24*/\
 277        MUX_VAL(CP(ETK_D11_ES2),    (IDIS | PTD | EN  | M4)) /*GPIO_25*/\
 278        MUX_VAL(CP(ETK_D12_ES2),    (IDIS | PTD | EN  | M4)) /*GPIO_26*/\
 279        MUX_VAL(CP(ETK_D13_ES2),    (IDIS | PTD | EN  | M4)) /*GPIO_27*/\
 280        MUX_VAL(CP(MCBSP1_CLKR),    (IEN  | PTD | DIS | M4)) /*GPIO_156*/\
 281        MUX_VAL(CP(MCBSP1_FSR),     (IEN  | PTU | EN  | M4)) /*GPIO_157*/\
 282        MUX_VAL(CP(MCBSP1_DX),      (IEN  | PTD | DIS | M4)) /*GPIO_158*/\
 283        MUX_VAL(CP(MCBSP1_DR),      (IDIS | PTD | DIS | M4)) /*GPIO_159*/\
 284        MUX_VAL(CP(MCBSP1_FSX),     (IEN  | PTD | DIS | M4)) /*GPIO_161*/\
 285        MUX_VAL(CP(MCBSP1_CLKX),    (IEN  | PTD | DIS | M4)) /*GPIO_162*/\
 286        MUX_VAL(CP(UART3_RTS_SD),   (IDIS | PTD | EN  | M4)) /*GPIO_164*/\
 287        MUX_VAL(CP(HDQ_SIO),        (IDIS | PTU | DIS | M4)) /*GPIO_170*/\
 288        MUX_VAL(CP(MCSPI1_CS3),     (IEN  | PTU | EN  | M4)) /*GPIO_177*/\
 289/*Control and debug */\
 290        MUX_VAL(CP(SYS_32K),        (IEN  | PTD | DIS | M0)) /*SYS_32K*/\
 291        MUX_VAL(CP(SYS_CLKREQ),     (IEN  | PTD | DIS | M0)) /*SYS_CLKREQ*/\
 292        MUX_VAL(CP(SYS_NIRQ),       (IEN  | PTU | EN  | M0)) /*SYS_nIRQ*/\
 293        MUX_VAL(CP(SYS_BOOT0),      (IEN  | PTD | DIS | M4)) /*GPIO_2*/\
 294        MUX_VAL(CP(SYS_BOOT1),      (IEN  | PTD | DIS | M4)) /*GPIO_3*/\
 295        MUX_VAL(CP(SYS_BOOT2),      (IEN  | PTD | DIS | M4)) /*GPIO_4*/\
 296        MUX_VAL(CP(SYS_BOOT3),      (IEN  | PTD | DIS | M4)) /*GPIO_5*/\
 297        MUX_VAL(CP(SYS_BOOT4),      (IEN  | PTD | DIS | M4)) /*GPIO_6*/\
 298        MUX_VAL(CP(SYS_BOOT6),      (IDIS | PTD | DIS | M4)) /*GPIO_8*/ \
 299        MUX_VAL(CP(SYS_OFF_MODE),   (IEN  | PTD | DIS | M0)) /*SYS_OFF_MODE*/\
 300        MUX_VAL(CP(SYS_CLKOUT1),    (IEN  | PTD | DIS | M0)) /*SYS_CLKOUT1*/\
 301        MUX_VAL(CP(SYS_CLKOUT2),    (IEN  | PTU | EN  | M4)) /*GPIO_186*/\
 302        MUX_VAL(CP(ETK_D8_ES2),     (IEN  | PTU | DIS | M3)) /*HSUSB1_DIR*/\
 303        MUX_VAL(CP(D2D_MCAD1),      (IEN  | PTD | EN  | M0)) /*d2d_mcad1*/\
 304        MUX_VAL(CP(D2D_MCAD2),      (IEN  | PTD | EN  | M0)) /*d2d_mcad2*/\
 305        MUX_VAL(CP(D2D_MCAD3),      (IEN  | PTD | EN  | M0)) /*d2d_mcad3*/\
 306        MUX_VAL(CP(D2D_MCAD4),      (IEN  | PTD | EN  | M0)) /*d2d_mcad4*/\
 307        MUX_VAL(CP(D2D_MCAD5),      (IEN  | PTD | EN  | M0)) /*d2d_mcad5*/\
 308        MUX_VAL(CP(D2D_MCAD6),      (IEN  | PTD | EN  | M0)) /*d2d_mcad6*/\
 309        MUX_VAL(CP(D2D_MCAD7),      (IEN  | PTD | EN  | M0)) /*d2d_mcad7*/\
 310        MUX_VAL(CP(D2D_MCAD8),      (IEN  | PTD | EN  | M0)) /*d2d_mcad8*/\
 311        MUX_VAL(CP(D2D_MCAD9),      (IEN  | PTD | EN  | M0)) /*d2d_mcad9*/\
 312        MUX_VAL(CP(D2D_MCAD10),     (IEN  | PTD | EN  | M0)) /*d2d_mcad10*/\
 313        MUX_VAL(CP(D2D_MCAD11),     (IEN  | PTD | EN  | M0)) /*d2d_mcad11*/\
 314        MUX_VAL(CP(D2D_MCAD12),     (IEN  | PTD | EN  | M0)) /*d2d_mcad12*/\
 315        MUX_VAL(CP(D2D_MCAD13),     (IEN  | PTD | EN  | M0)) /*d2d_mcad13*/\
 316        MUX_VAL(CP(D2D_MCAD14),     (IEN  | PTD | EN  | M0)) /*d2d_mcad14*/\
 317        MUX_VAL(CP(D2D_MCAD15),     (IEN  | PTD | EN  | M0)) /*d2d_mcad15*/\
 318        MUX_VAL(CP(D2D_MCAD16),     (IEN  | PTD | EN  | M0)) /*d2d_mcad16*/\
 319        MUX_VAL(CP(D2D_MCAD17),     (IEN  | PTD | EN  | M0)) /*d2d_mcad17*/\
 320        MUX_VAL(CP(D2D_MCAD18),     (IEN  | PTD | EN  | M0)) /*d2d_mcad18*/\
 321        MUX_VAL(CP(D2D_MCAD19),     (IEN  | PTD | EN  | M0)) /*d2d_mcad19*/\
 322        MUX_VAL(CP(D2D_MCAD20),     (IEN  | PTD | EN  | M0)) /*d2d_mcad20*/\
 323        MUX_VAL(CP(D2D_MCAD21),     (IEN  | PTD | EN  | M0)) /*d2d_mcad21*/\
 324        MUX_VAL(CP(D2D_MCAD22),     (IEN  | PTD | EN  | M0)) /*d2d_mcad22*/\
 325        MUX_VAL(CP(D2D_MCAD23),     (IEN  | PTD | EN  | M0)) /*d2d_mcad23*/\
 326        MUX_VAL(CP(D2D_MCAD24),     (IEN  | PTD | EN  | M0)) /*d2d_mcad24*/\
 327        MUX_VAL(CP(D2D_MCAD25),     (IEN  | PTD | EN  | M0)) /*d2d_mcad25*/\
 328        MUX_VAL(CP(D2D_MCAD26),     (IEN  | PTD | EN  | M0)) /*d2d_mcad26*/\
 329        MUX_VAL(CP(D2D_MCAD27),     (IEN  | PTD | EN  | M0)) /*d2d_mcad27*/\
 330        MUX_VAL(CP(D2D_MCAD28),     (IEN  | PTD | EN  | M0)) /*d2d_mcad28*/\
 331        MUX_VAL(CP(D2D_MCAD29),     (IEN  | PTD | EN  | M0)) /*d2d_mcad29*/\
 332        MUX_VAL(CP(D2D_MCAD30),     (IEN  | PTD | EN  | M0)) /*d2d_mcad30*/\
 333        MUX_VAL(CP(D2D_MCAD31),     (IEN  | PTD | EN  | M0)) /*d2d_mcad31*/\
 334        MUX_VAL(CP(D2D_MCAD32),     (IEN  | PTD | EN  | M0)) /*d2d_mcad32*/\
 335        MUX_VAL(CP(D2D_MCAD33),     (IEN  | PTD | EN  | M0)) /*d2d_mcad33*/\
 336        MUX_VAL(CP(D2D_MCAD34),     (IEN  | PTD | EN  | M0)) /*d2d_mcad34*/\
 337        MUX_VAL(CP(D2D_MCAD35),     (IEN  | PTD | EN  | M0)) /*d2d_mcad35*/\
 338        MUX_VAL(CP(D2D_MCAD36),     (IEN  | PTD | EN  | M0)) /*d2d_mcad36*/\
 339        MUX_VAL(CP(D2D_CLK26MI),    (IEN  | PTD | DIS | M0)) /*d2d_clk26mi*/\
 340        MUX_VAL(CP(D2D_NRESPWRON),  (IEN  | PTD | EN  | M0)) /*d2d_nrespwron*/\
 341        MUX_VAL(CP(D2D_NRESWARM),   (IEN  | PTU | EN  | M0)) /*d2d_nreswarm */\
 342        MUX_VAL(CP(D2D_ARM9NIRQ),   (IEN  | PTD | DIS | M0)) /*d2d_arm9nirq */\
 343        MUX_VAL(CP(D2D_UMA2P6FIQ),  (IEN  | PTD | DIS | M0)) /*d2d_uma2p6fiq*/\
 344        MUX_VAL(CP(D2D_SPINT),      (IEN  | PTD | EN  | M0)) /*d2d_spint*/\
 345        MUX_VAL(CP(D2D_FRINT),      (IEN  | PTD | EN  | M0)) /*d2d_frint*/\
 346        MUX_VAL(CP(D2D_DMAREQ0),    (IEN  | PTD | DIS | M0)) /*d2d_dmareq0*/\
 347        MUX_VAL(CP(D2D_DMAREQ1),    (IEN  | PTD | DIS | M0)) /*d2d_dmareq1*/\
 348        MUX_VAL(CP(D2D_DMAREQ2),    (IEN  | PTD | DIS | M0)) /*d2d_dmareq2*/\
 349        MUX_VAL(CP(D2D_DMAREQ3),    (IEN  | PTD | DIS | M0)) /*d2d_dmareq3*/\
 350        MUX_VAL(CP(D2D_N3GTRST),    (IEN  | PTD | DIS | M0)) /*d2d_n3gtrst*/\
 351        MUX_VAL(CP(D2D_N3GTDI),     (IEN  | PTD | DIS | M0)) /*d2d_n3gtdi*/\
 352        MUX_VAL(CP(D2D_N3GTDO),     (IEN  | PTD | DIS | M0)) /*d2d_n3gtdo*/\
 353        MUX_VAL(CP(D2D_N3GTMS),     (IEN  | PTD | DIS | M0)) /*d2d_n3gtms*/\
 354        MUX_VAL(CP(D2D_N3GTCK),     (IEN  | PTD | DIS | M0)) /*d2d_n3gtck*/\
 355        MUX_VAL(CP(D2D_N3GRTCK),    (IEN  | PTD | DIS | M0)) /*d2d_n3grtck*/\
 356        MUX_VAL(CP(D2D_MSTDBY),     (IEN  | PTU | EN  | M0)) /*d2d_mstdby*/\
 357        MUX_VAL(CP(D2D_SWAKEUP),    (IEN  | PTD | EN  | M0)) /*d2d_swakeup*/\
 358        MUX_VAL(CP(D2D_IDLEREQ),    (IEN  | PTD | DIS | M0)) /*d2d_idlereq*/\
 359        MUX_VAL(CP(D2D_IDLEACK),    (IEN  | PTU | EN  | M0)) /*d2d_idleack*/\
 360        MUX_VAL(CP(D2D_MWRITE),     (IEN  | PTD | DIS | M0)) /*d2d_mwrite*/\
 361        MUX_VAL(CP(D2D_SWRITE),     (IEN  | PTD | DIS | M0)) /*d2d_swrite*/\
 362        MUX_VAL(CP(D2D_MREAD),      (IEN  | PTD | DIS | M0)) /*d2d_mread*/\
 363        MUX_VAL(CP(D2D_SREAD),      (IEN  | PTD | DIS | M0)) /*d2d_sread*/\
 364        MUX_VAL(CP(D2D_MBUSFLAG),   (IEN  | PTD | DIS | M0)) /*d2d_mbusflag*/\
 365        MUX_VAL(CP(D2D_SBUSFLAG),   (IEN  | PTD | DIS | M0)) /*d2d_sbusflag */
 366
 367#endif
 368
Hosted by Missing Link Electronics. The original LXR software by the LXR community, this experimental version by lxr@linux.no.