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11#include <common.h>
12#include <spl.h>
13#include <asm/io.h>
14#include <asm/gpio.h>
15#include <asm/arch/mx6-ddr.h>
16#include <asm/arch/clock.h>
17#include <asm/arch/sys_proto.h>
18#include <asm/arch/crm_regs.h>
19#include <asm/imx-common/iomux-v3.h>
20#include <fsl_esdhc.h>
21#include "common.h"
22
23DECLARE_GLOBAL_DATA_PTR;
24
25enum ddr_config {
26 DDR_16BIT_256MB,
27 DDR_32BIT_512MB,
28 DDR_32BIT_1GB,
29 DDR_64BIT_1GB,
30 DDR_64BIT_2GB,
31 DDR_64BIT_4GB,
32 DDR_UNKNOWN,
33};
34
35
36
37
38
39
40
41#define CM_FX6_DDR_IOMUX_CFG \
42 .dram_sdqs0 = 0x00000038, \
43 .dram_sdqs1 = 0x00000038, \
44 .dram_sdqs2 = 0x00000038, \
45 .dram_sdqs3 = 0x00000038, \
46 .dram_sdqs4 = 0x00000038, \
47 .dram_sdqs5 = 0x00000038, \
48 .dram_sdqs6 = 0x00000038, \
49 .dram_sdqs7 = 0x00000038, \
50 .dram_dqm0 = 0x00000038, \
51 .dram_dqm1 = 0x00000038, \
52 .dram_dqm2 = 0x00000038, \
53 .dram_dqm3 = 0x00000038, \
54 .dram_dqm4 = 0x00000038, \
55 .dram_dqm5 = 0x00000038, \
56 .dram_dqm6 = 0x00000038, \
57 .dram_dqm7 = 0x00000038, \
58 .dram_cas = 0x00000038, \
59 .dram_ras = 0x00000038, \
60 .dram_sdclk_0 = 0x00000038, \
61 .dram_sdclk_1 = 0x00000038, \
62 .dram_sdcke0 = 0x00003000, \
63 .dram_sdcke1 = 0x00003000, \
64 .dram_reset = 0x00000038, \
65 .dram_sdba2 = 0x00000000, \
66 .dram_sdodt0 = 0x00000038, \
67 .dram_sdodt1 = 0x00000038,
68
69#define CM_FX6_GPR_IOMUX_CFG \
70 .grp_b0ds = 0x00000038, \
71 .grp_b1ds = 0x00000038, \
72 .grp_b2ds = 0x00000038, \
73 .grp_b3ds = 0x00000038, \
74 .grp_b4ds = 0x00000038, \
75 .grp_b5ds = 0x00000038, \
76 .grp_b6ds = 0x00000038, \
77 .grp_b7ds = 0x00000038, \
78 .grp_addds = 0x00000038, \
79 .grp_ddrmode_ctl = 0x00020000, \
80 .grp_ddrpke = 0x00000000, \
81 .grp_ddrmode = 0x00020000, \
82 .grp_ctlds = 0x00000038, \
83 .grp_ddr_type = 0x000C0000,
84
85static struct mx6sdl_iomux_ddr_regs ddr_iomux_s = { CM_FX6_DDR_IOMUX_CFG };
86static struct mx6sdl_iomux_grp_regs grp_iomux_s = { CM_FX6_GPR_IOMUX_CFG };
87static struct mx6dq_iomux_ddr_regs ddr_iomux_q = { CM_FX6_DDR_IOMUX_CFG };
88static struct mx6dq_iomux_grp_regs grp_iomux_q = { CM_FX6_GPR_IOMUX_CFG };
89
90static struct mx6_mmdc_calibration cm_fx6_calib_s = {
91 .p0_mpwldectrl0 = 0x005B0061,
92 .p0_mpwldectrl1 = 0x004F0055,
93 .p0_mpdgctrl0 = 0x0314030C,
94 .p0_mpdgctrl1 = 0x025C0268,
95 .p0_mprddlctl = 0x42464646,
96 .p0_mpwrdlctl = 0x36322C34,
97};
98
99static struct mx6_ddr_sysinfo cm_fx6_sysinfo_s = {
100 .cs1_mirror = 1,
101 .cs_density = 16,
102 .bi_on = 1,
103 .rtt_nom = 1,
104 .rtt_wr = 0,
105 .ralat = 5,
106 .walat = 1,
107 .mif3_mode = 3,
108 .rst_to_cke = 0x23,
109 .sde_to_rst = 0x10,
110};
111
112static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_s = {
113 .mem_speed = 800,
114 .density = 4,
115 .rowaddr = 14,
116 .coladdr = 10,
117 .pagesz = 2,
118 .trcd = 1800,
119 .trcmin = 5200,
120 .trasmin = 3600,
121 .SRT = 0,
122};
123
124static void spl_mx6s_dram_init(enum ddr_config dram_config, bool reset)
125{
126 if (reset)
127 ((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2;
128
129 switch (dram_config) {
130 case DDR_16BIT_256MB:
131 cm_fx6_sysinfo_s.dsize = 0;
132 cm_fx6_sysinfo_s.ncs = 1;
133 break;
134 case DDR_32BIT_512MB:
135 cm_fx6_sysinfo_s.dsize = 1;
136 cm_fx6_sysinfo_s.ncs = 1;
137 break;
138 case DDR_32BIT_1GB:
139 cm_fx6_sysinfo_s.dsize = 1;
140 cm_fx6_sysinfo_s.ncs = 2;
141 break;
142 default:
143 puts("Tried to setup invalid DDR configuration\n");
144 hang();
145 }
146
147 mx6_dram_cfg(&cm_fx6_sysinfo_s, &cm_fx6_calib_s, &cm_fx6_ddr3_cfg_s);
148 udelay(100);
149}
150
151static struct mx6_mmdc_calibration cm_fx6_calib_q = {
152 .p0_mpwldectrl0 = 0x00630068,
153 .p0_mpwldectrl1 = 0x0068005D,
154 .p0_mpdgctrl0 = 0x04140428,
155 .p0_mpdgctrl1 = 0x037C037C,
156 .p0_mprddlctl = 0x3C30303A,
157 .p0_mpwrdlctl = 0x3A344038,
158 .p1_mpwldectrl0 = 0x0035004C,
159 .p1_mpwldectrl1 = 0x00170026,
160 .p1_mpdgctrl0 = 0x0374037C,
161 .p1_mpdgctrl1 = 0x0350032C,
162 .p1_mprddlctl = 0x30322A3C,
163 .p1_mpwrdlctl = 0x48304A3E,
164};
165
166static struct mx6_ddr_sysinfo cm_fx6_sysinfo_q = {
167 .cs_density = 16,
168 .cs1_mirror = 1,
169 .bi_on = 1,
170 .rtt_nom = 1,
171 .rtt_wr = 0,
172 .ralat = 5,
173 .walat = 1,
174 .mif3_mode = 3,
175 .rst_to_cke = 0x23,
176 .sde_to_rst = 0x10,
177};
178
179static struct mx6_ddr3_cfg cm_fx6_ddr3_cfg_q = {
180 .mem_speed = 1066,
181 .density = 4,
182 .rowaddr = 14,
183 .coladdr = 10,
184 .pagesz = 2,
185 .trcd = 1324,
186 .trcmin = 59500,
187 .trasmin = 9750,
188 .SRT = 0,
189};
190
191static void spl_mx6q_dram_init(enum ddr_config dram_config, bool reset)
192{
193 if (reset)
194 ((struct mmdc_p_regs *)MX6_MMDC_P0_MDCTL)->mdmisc = 2;
195
196 cm_fx6_ddr3_cfg_q.rowaddr = 14;
197 switch (dram_config) {
198 case DDR_16BIT_256MB:
199 cm_fx6_sysinfo_q.dsize = 0;
200 cm_fx6_sysinfo_q.ncs = 1;
201 break;
202 case DDR_32BIT_512MB:
203 cm_fx6_sysinfo_q.dsize = 1;
204 cm_fx6_sysinfo_q.ncs = 1;
205 break;
206 case DDR_64BIT_1GB:
207 cm_fx6_sysinfo_q.dsize = 2;
208 cm_fx6_sysinfo_q.ncs = 1;
209 break;
210 case DDR_64BIT_2GB:
211 cm_fx6_sysinfo_q.dsize = 2;
212 cm_fx6_sysinfo_q.ncs = 2;
213 break;
214 case DDR_64BIT_4GB:
215 cm_fx6_sysinfo_q.dsize = 2;
216 cm_fx6_sysinfo_q.ncs = 2;
217 cm_fx6_ddr3_cfg_q.rowaddr = 15;
218 break;
219 default:
220 puts("Tried to setup invalid DDR configuration\n");
221 hang();
222 }
223
224 mx6_dram_cfg(&cm_fx6_sysinfo_q, &cm_fx6_calib_q, &cm_fx6_ddr3_cfg_q);
225 udelay(100);
226}
227
228static int cm_fx6_spl_dram_init(void)
229{
230 unsigned long bank1_size, bank2_size;
231
232 switch (get_cpu_type()) {
233 case MXC_CPU_MX6SOLO:
234 mx6sdl_dram_iocfg(64, &ddr_iomux_s, &grp_iomux_s);
235
236 spl_mx6s_dram_init(DDR_32BIT_1GB, false);
237 bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
238 bank2_size = get_ram_size((long int *)PHYS_SDRAM_2, 0x80000000);
239 if (bank1_size == 0x20000000) {
240 if (bank2_size == 0x20000000)
241 return 0;
242
243 spl_mx6s_dram_init(DDR_32BIT_512MB, true);
244 return 0;
245 }
246
247 spl_mx6s_dram_init(DDR_16BIT_256MB, true);
248 bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
249 if (bank1_size == 0x10000000)
250 return 0;
251
252 break;
253 case MXC_CPU_MX6D:
254 case MXC_CPU_MX6Q:
255 mx6dq_dram_iocfg(64, &ddr_iomux_q, &grp_iomux_q);
256
257 spl_mx6q_dram_init(DDR_64BIT_4GB, false);
258 bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
259 if (bank1_size == 0x80000000)
260 return 0;
261
262 if (bank1_size == 0x40000000) {
263 bank2_size = get_ram_size((long int *)PHYS_SDRAM_2,
264 0x80000000);
265 if (bank2_size == 0x40000000) {
266
267 spl_mx6q_dram_init(DDR_64BIT_2GB, false);
268 } else {
269 spl_mx6q_dram_init(DDR_64BIT_1GB, true);
270 }
271
272 return 0;
273 }
274
275 spl_mx6q_dram_init(DDR_32BIT_512MB, true);
276 bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
277 if (bank1_size == 0x20000000)
278 return 0;
279
280 spl_mx6q_dram_init(DDR_16BIT_256MB, true);
281 bank1_size = get_ram_size((long int *)PHYS_SDRAM_1, 0x80000000);
282 if (bank1_size == 0x10000000)
283 return 0;
284
285 break;
286 }
287
288 return -1;
289}
290
291static iomux_v3_cfg_t const uart4_pads[] = {
292 IOMUX_PADS(PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
293 IOMUX_PADS(PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
294};
295
296static void cm_fx6_setup_uart(void)
297{
298 SETUP_IOMUX_PADS(uart4_pads);
299 enable_uart_clk(1);
300}
301
302#ifdef CONFIG_SPL_SPI_SUPPORT
303static void cm_fx6_setup_ecspi(void)
304{
305 cm_fx6_set_ecspi_iomux();
306 enable_cspi_clock(1, 0);
307}
308#else
309static void cm_fx6_setup_ecspi(void) { }
310#endif
311
312void board_init_f(ulong dummy)
313{
314 struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
315
316 gd = &gdata;
317
318
319
320
321
322 setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK);
323 enable_usdhc_clk(1, 2);
324
325 arch_cpu_init();
326 timer_init();
327 cm_fx6_setup_ecspi();
328 cm_fx6_setup_uart();
329 get_clocks();
330 preloader_console_init();
331 gpio_direction_output(CM_FX6_GREEN_LED, 1);
332 if (cm_fx6_spl_dram_init()) {
333 puts("!!!ERROR!!! DRAM detection failed!!!\n");
334 hang();
335 }
336
337 memset(__bss_start, 0, __bss_end - __bss_start);
338 board_init_r(NULL, 0);
339}
340
341void spl_board_init(void)
342{
343 u32 boot_device = spl_boot_device();
344
345 if (boot_device == BOOT_DEVICE_SPI)
346 puts("Booting from SPI flash\n");
347 else if (boot_device == BOOT_DEVICE_MMC1)
348 puts("Booting from MMC\n");
349 else
350 puts("Unknown boot device\n");
351}
352
353#ifdef CONFIG_SPL_MMC_SUPPORT
354static struct fsl_esdhc_cfg usdhc_cfg = {
355 .esdhc_base = USDHC3_BASE_ADDR,
356 .max_bus_width = 4,
357};
358
359int board_mmc_init(bd_t *bis)
360{
361 cm_fx6_set_usdhc_iomux();
362
363 usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
364
365 return fsl_esdhc_initialize(bis, &usdhc_cfg);
366}
367#endif
368
