LXR uboot/board/esd/otc570/otc570.c

   1/*
   2 * (C) Copyright 2010-2011
   3 * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
   4 * esd electronic system design gmbh <www.esd.eu>
   5 *
   6 * (C) Copyright 2007-2008
   7 * Stelian Pop <stelian@popies.net>
   8 * Lead Tech Design <www.leadtechdesign.com>
   9 *
  10 * SPDX-License-Identifier:     GPL-2.0+
  11 */
  12
  13#include <common.h>
  14#include <asm/io.h>
  15#include <asm/gpio.h>
  16#include <asm/arch/at91sam9_smc.h>
  17#include <asm/arch/at91_common.h>
  18#include <asm/arch/at91_pmc.h>
  19#include <asm/arch/at91_rstc.h>
  20#include <asm/arch/at91_matrix.h>
  21#include <asm/arch/at91_pio.h>
  22#include <asm/arch/clk.h>
  23#include <netdev.h>
  24#ifdef CONFIG_LCD
  25# include <atmel_lcdc.h>
  26# include <lcd.h>
  27# ifdef CONFIG_LCD_INFO
  28#  include <nand.h>
  29#  include <version.h>
  30# endif
  31#endif
  32
  33DECLARE_GLOBAL_DATA_PTR;
  34
  35/*
  36 * Miscelaneous platform dependent initialisations
  37 */
  38
  39static int hw_rev = -1; /* hardware revision */
  40
  41int get_hw_rev(void)
  42{
  43        if (hw_rev >= 0)
  44                return hw_rev;
  45
  46        hw_rev = at91_get_pio_value(AT91_PIO_PORTB, 19);
  47        hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 20) << 1;
  48        hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 21) << 2;
  49        hw_rev |= at91_get_pio_value(AT91_PIO_PORTB, 22) << 3;
  50
  51        if (hw_rev == 15)
  52                hw_rev = 0;
  53
  54        return hw_rev;
  55}
  56
  57#ifdef CONFIG_CMD_NAND
  58static void otc570_nand_hw_init(void)
  59{
  60        unsigned long csa;
  61        at91_smc_t      *smc    = (at91_smc_t *) ATMEL_BASE_SMC0;
  62        at91_matrix_t   *matrix = (at91_matrix_t *) ATMEL_BASE_MATRIX;
  63
  64        /* Enable CS3 */
  65        csa = readl(&matrix->csa[0]) | AT91_MATRIX_CSA_EBI_CS3A;
  66        writel(csa, &matrix->csa[0]);
  67
  68        /* Configure SMC CS3 for NAND/SmartMedia */
  69        writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(1) |
  70                AT91_SMC_SETUP_NRD(2) | AT91_SMC_SETUP_NCS_RD(2),
  71                &smc->cs[3].setup);
  72
  73        writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  74                AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  75                &smc->cs[3].pulse);
  76
  77        writel(AT91_SMC_CYCLE_NWE(6) | AT91_SMC_CYCLE_NRD(6),
  78                &smc->cs[3].cycle);
  79        writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  80                AT91_SMC_MODE_EXNW_DISABLE |
  81                AT91_SMC_MODE_DBW_8 |
  82                AT91_SMC_MODE_TDF_CYCLE(12),
  83                &smc->cs[3].mode);
  84
  85        /* Configure RDY/BSY */
  86        gpio_direction_input(CONFIG_SYS_NAND_READY_PIN);
  87
  88        /* Enable NandFlash */
  89        gpio_direction_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  90}
  91#endif /* CONFIG_CMD_NAND */
  92
  93#ifdef CONFIG_MACB
  94static void otc570_macb_hw_init(void)
  95{
  96        at91_pmc_t      *pmc    = (at91_pmc_t *) ATMEL_BASE_PMC;
  97        /* Enable clock */
  98        writel(1 << ATMEL_ID_EMAC, &pmc->pcer);
  99        at91_macb_hw_init();
 100}
 101#endif
 102
 103/*
 104 * Static memory controller initialization to enable Beckhoff ET1100 EtherCAT
 105 * controller debugging
 106 * The ET1100 is located at physical address 0x70000000
 107 * Its process memory is located at physical address 0x70001000
 108 */
 109static void otc570_ethercat_hw_init(void)
 110{
 111        at91_smc_t      *smc1   = (at91_smc_t *) ATMEL_BASE_SMC1;
 112
 113        /* Configure SMC EBI1_CS0 for EtherCAT */
 114        writel(AT91_SMC_SETUP_NWE(0) | AT91_SMC_SETUP_NCS_WR(0) |
 115                AT91_SMC_SETUP_NRD(0) | AT91_SMC_SETUP_NCS_RD(0),
 116                &smc1->cs[0].setup);
 117        writel(AT91_SMC_PULSE_NWE(4) | AT91_SMC_PULSE_NCS_WR(9) |
 118                AT91_SMC_PULSE_NRD(5) | AT91_SMC_PULSE_NCS_RD(9),
 119                &smc1->cs[0].pulse);
 120        writel(AT91_SMC_CYCLE_NWE(10) | AT91_SMC_CYCLE_NRD(6),
 121                &smc1->cs[0].cycle);
 122        /*
 123         * Configure behavior at external wait signal, byte-select mode, 16 bit
 124         * data bus width, none data float wait states and TDF optimization
 125         */
 126        writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_EXNW_READY |
 127                AT91_SMC_MODE_DBW_16 | AT91_SMC_MODE_TDF_CYCLE(0) |
 128                AT91_SMC_MODE_TDF, &smc1->cs[0].mode);
 129
 130        /* Configure RDY/BSY */
 131        at91_set_b_periph(AT91_PIO_PORTE, 20, 0);       /* EBI1_NWAIT */
 132}
 133
 134#ifdef CONFIG_LCD
 135/* Number of columns and rows, pixel clock in Hz and hsync/vsync polarity */
 136vidinfo_t panel_info = {
 137        .vl_col =               640,
 138        .vl_row =               480,
 139        .vl_clk =               25175000,
 140        .vl_sync =              ATMEL_LCDC_INVLINE_INVERTED |
 141                                ATMEL_LCDC_INVFRAME_INVERTED,
 142
 143        .vl_bpix =              LCD_BPP,/* Bits per pixel, 0 = 1bit, 3 = 8bit */
 144        .vl_tft =               1,      /* 0 = passive, 1 = TFT */
 145        .vl_vsync_len =         1,      /* Length of vertical sync in NOL */
 146        .vl_upper_margin =      35,     /* Idle lines at the frame start */
 147        .vl_lower_margin =      5,      /* Idle lines at the end of the frame */
 148        .vl_hsync_len =         5,      /* Width of the LCDHSYNC pulse */
 149        .vl_left_margin =       112,    /* Idle cycles at the line beginning */
 150        .vl_right_margin =      1,      /* Idle cycles at the end of the line */
 151
 152        .mmio =                 ATMEL_BASE_LCDC,
 153};
 154
 155void lcd_enable(void)
 156{
 157        at91_set_pio_value(AT91_PIO_PORTA, 30, 0); /* power up */
 158}
 159
 160void lcd_disable(void)
 161{
 162        at91_set_pio_value(AT91_PIO_PORTA, 30, 1); /* power down */
 163}
 164
 165static void otc570_lcd_hw_init(void)
 166{
 167        at91_pmc_t      *pmc    = (at91_pmc_t *) ATMEL_BASE_PMC;
 168
 169        at91_set_a_periph(AT91_PIO_PORTC, 0, 0);        /* LCDVSYNC */
 170        at91_set_a_periph(AT91_PIO_PORTC, 1, 0);        /* LCDHSYNC */
 171        at91_set_a_periph(AT91_PIO_PORTC, 2, 0);        /* LCDDOTCK */
 172        at91_set_a_periph(AT91_PIO_PORTC, 3, 0);        /* LCDDEN */
 173        at91_set_b_periph(AT91_PIO_PORTB, 9, 0);        /* LCDCC */
 174        at91_set_a_periph(AT91_PIO_PORTC, 6, 0);        /* LCDD2 */
 175        at91_set_a_periph(AT91_PIO_PORTC, 7, 0);        /* LCDD3 */
 176        at91_set_a_periph(AT91_PIO_PORTC, 8, 0);        /* LCDD4 */
 177        at91_set_a_periph(AT91_PIO_PORTC, 9, 0);        /* LCDD5 */
 178        at91_set_a_periph(AT91_PIO_PORTC, 10, 0);       /* LCDD6 */
 179        at91_set_a_periph(AT91_PIO_PORTC, 11, 0);       /* LCDD7 */
 180        at91_set_a_periph(AT91_PIO_PORTC, 14, 0);       /* LCDD10 */
 181        at91_set_a_periph(AT91_PIO_PORTC, 15, 0);       /* LCDD11 */
 182        at91_set_a_periph(AT91_PIO_PORTC, 16, 0);       /* LCDD12 */
 183        at91_set_b_periph(AT91_PIO_PORTC, 12, 0);       /* LCDD13 */
 184        at91_set_a_periph(AT91_PIO_PORTC, 18, 0);       /* LCDD14 */
 185        at91_set_a_periph(AT91_PIO_PORTC, 19, 0);       /* LCDD15 */
 186        at91_set_a_periph(AT91_PIO_PORTC, 22, 0);       /* LCDD18 */
 187        at91_set_a_periph(AT91_PIO_PORTC, 23, 0);       /* LCDD19 */
 188        at91_set_a_periph(AT91_PIO_PORTC, 24, 0);       /* LCDD20 */
 189        at91_set_b_periph(AT91_PIO_PORTC, 17, 0);       /* LCDD21 */
 190        at91_set_a_periph(AT91_PIO_PORTC, 26, 0);       /* LCDD22 */
 191        at91_set_a_periph(AT91_PIO_PORTC, 27, 0);       /* LCDD23 */
 192        at91_set_pio_output(AT91_PIO_PORTA, 30, 1);     /* PCI */
 193
 194        writel(1 << ATMEL_ID_LCDC, &pmc->pcer);
 195}
 196
 197#ifdef CONFIG_LCD_INFO
 198void lcd_show_board_info(void)
 199{
 200        ulong dram_size, nand_size;
 201        int i;
 202        char temp[32];
 203
 204        dram_size = 0;
 205        for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 206                dram_size += gd->bd->bi_dram[i].size;
 207        nand_size = 0;
 208        for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
 209                nand_size += nand_info[i].size;
 210
 211        lcd_printf("\n%s\n", U_BOOT_VERSION);
 212        lcd_printf("CPU at %s MHz\n", strmhz(temp, get_cpu_clk_rate()));
 213        lcd_printf("  %ld MB SDRAM, %ld MB NAND\n",
 214                dram_size >> 20,
 215                nand_size >> 20 );
 216        lcd_printf("  Board            : esd ARM9 HMI Panel - OTC570\n");
 217        lcd_printf("  Hardware-revision: 1.%d\n", get_hw_rev());
 218        lcd_printf("  Mach-type        : %lu\n", gd->bd->bi_arch_number);
 219}
 220#endif /* CONFIG_LCD_INFO */
 221#endif /* CONFIG_LCD */
 222
 223int dram_init(void)
 224{
 225        gd->ram_size = get_ram_size(
 226                (void *)CONFIG_SYS_SDRAM_BASE,
 227                CONFIG_SYS_SDRAM_SIZE);
 228        return 0;
 229}
 230
 231int board_eth_init(bd_t *bis)
 232{
 233        int rc = 0;
 234#ifdef CONFIG_MACB
 235        rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC, 0x00);
 236#endif
 237        return rc;
 238}
 239
 240int checkboard(void)
 241{
 242        char str[32];
 243
 244        puts("Board            : esd ARM9 HMI Panel - OTC570");
 245        if (getenv_f("serial#", str, sizeof(str)) > 0) {
 246                puts(", serial# ");
 247                puts(str);
 248        }
 249        printf("\n");
 250        printf("Hardware-revision: 1.%d\n", get_hw_rev());
 251        printf("Mach-type        : %lu\n", gd->bd->bi_arch_number);
 252        return 0;
 253}
 254
 255#ifdef CONFIG_SERIAL_TAG
 256void get_board_serial(struct tag_serialnr *serialnr)
 257{
 258        char *str;
 259
 260        char *serial = getenv("serial#");
 261        if (serial) {
 262                str = strchr(serial, '_');
 263                if (str && (strlen(str) >= 4)) {
 264                        serialnr->high = (*(str + 1) << 8) | *(str + 2);
 265                        serialnr->low = simple_strtoul(str + 3, NULL, 16);
 266                }
 267        } else {
 268                serialnr->high = 0;
 269                serialnr->low = 0;
 270        }
 271}
 272#endif
 273
 274#ifdef CONFIG_REVISION_TAG
 275u32 get_board_rev(void)
 276{
 277        return hw_rev | 0x100;
 278}
 279#endif
 280
 281#ifdef CONFIG_MISC_INIT_R
 282int misc_init_r(void)
 283{
 284        char            str[64];
 285        at91_pmc_t      *pmc    = (at91_pmc_t *) ATMEL_BASE_PMC;
 286
 287        at91_set_pio_output(AT91_PIO_PORTA, 29, 1);
 288        at91_set_a_periph(AT91_PIO_PORTA, 26, 1);       /* TXD0 */
 289        at91_set_a_periph(AT91_PIO_PORTA, 27, 0);       /* RXD0 */
 290        writel(1 << ATMEL_ID_USART0, &pmc->pcer);
 291        /* Set USART_MODE = 1 (RS485) */
 292        writel(1, 0xFFF8C004);
 293
 294        printf("USART0: ");
 295
 296        if (getenv_f("usart0", str, sizeof(str)) == -1) {
 297                printf("No entry - assuming 1-wire\n");
 298                /* CTS pin, works as mode select pin (0 = 1-wire; 1 = RS485) */
 299                at91_set_pio_output(AT91_PIO_PORTA, 29, 0);
 300        } else {
 301                if (strcmp(str, "1-wire") == 0) {
 302                        printf("%s\n", str);
 303                        at91_set_pio_output(AT91_PIO_PORTA, 29, 0);
 304                } else if (strcmp(str, "rs485") == 0) {
 305                        printf("%s\n", str);
 306                        at91_set_pio_output(AT91_PIO_PORTA, 29, 1);
 307                } else {
 308                        printf("Wrong entry - assuming 1-wire ");
 309                        printf("(valid values are '1-wire' or 'rs485')\n");
 310                        at91_set_pio_output(AT91_PIO_PORTA, 29, 0);
 311                }
 312        }
 313#ifdef CONFIG_LCD
 314        printf("Display memory address: 0x%08lX\n", gd->fb_base);
 315#endif
 316
 317        return 0;
 318}
 319#endif /* CONFIG_MISC_INIT_R */
 320
 321int board_early_init_f(void)
 322{
 323        at91_pmc_t      *pmc    = (at91_pmc_t *) ATMEL_BASE_PMC;
 324
 325        /* enable all clocks */
 326        writel((1 << ATMEL_ID_PIOA) |
 327                (1 << ATMEL_ID_PIOB) |
 328                (1 << ATMEL_ID_PIOCDE) |
 329                (1 << ATMEL_ID_TWI) |
 330                (1 << ATMEL_ID_SPI0) |
 331#ifdef CONFIG_LCD
 332                (1 << ATMEL_ID_LCDC) |
 333#endif
 334                (1 << ATMEL_ID_UHP),
 335                &pmc->pcer);
 336
 337        at91_seriald_hw_init();
 338
 339        /* arch number of OTC570-Board */
 340        gd->bd->bi_arch_number = MACH_TYPE_OTC570;
 341
 342        return 0;
 343}
 344
 345int board_init(void)
 346{
 347        /* initialize ET1100 Controller */
 348        otc570_ethercat_hw_init();
 349
 350        /* adress of boot parameters */
 351        gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 352
 353#ifdef CONFIG_CMD_NAND
 354        otc570_nand_hw_init();
 355#endif
 356#ifdef CONFIG_HAS_DATAFLASH
 357        at91_spi0_hw_init(1 << 0);
 358#endif
 359#ifdef CONFIG_MACB
 360        otc570_macb_hw_init();
 361#endif
 362#ifdef CONFIG_AT91_CAN
 363        at91_can_hw_init();
 364#endif
 365#ifdef CONFIG_USB_OHCI_NEW
 366        at91_uhp_hw_init();
 367#endif
 368#ifdef CONFIG_LCD
 369        otc570_lcd_hw_init();
 370#endif
 371        return 0;
 372}
 373