LXR uboot/board/freescale/m5282evb/m5282evb.c

   1/*
   2 * (C) Copyright 2000-2003
   3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8#include <common.h>
   9#include <asm/immap.h>
  10
  11DECLARE_GLOBAL_DATA_PTR;
  12
  13int checkboard (void)
  14{
  15        puts ("Board: Freescale M5282EVB Evaluation Board\n");
  16        return 0;
  17}
  18
  19phys_size_t initdram (int board_type)
  20{
  21        u32 dramsize, i, dramclk;
  22
  23        dramsize = CONFIG_SYS_SDRAM_SIZE * 0x100000;
  24        for (i = 0x13; i < 0x20; i++) {
  25                if (dramsize == (1 << i))
  26                        break;
  27        }
  28        i--;
  29
  30        if (!(MCFSDRAMC_DACR0 & MCFSDRAMC_DACR_RE))
  31        {
  32                dramclk = gd->bus_clk / (CONFIG_SYS_HZ * CONFIG_SYS_HZ);
  33
  34                /* Initialize DRAM Control Register: DCR */
  35                MCFSDRAMC_DCR = (0
  36                        | MCFSDRAMC_DCR_RTIM_6
  37                        | MCFSDRAMC_DCR_RC((15 * dramclk)>>4));
  38                asm("nop");
  39
  40                /* Initialize DACR0 */
  41                MCFSDRAMC_DACR0 = (0
  42                        | MCFSDRAMC_DACR_BASE(CONFIG_SYS_SDRAM_BASE)
  43                        | MCFSDRAMC_DACR_CASL(1)
  44                        | MCFSDRAMC_DACR_CBM(3)
  45                        | MCFSDRAMC_DACR_PS_32);
  46                asm("nop");
  47
  48                /* Initialize DMR0 */
  49                MCFSDRAMC_DMR0 = (0
  50                        | ((dramsize - 1) & 0xFFFC0000)
  51                        | MCFSDRAMC_DMR_V);
  52                asm("nop");
  53
  54                /* Set IP (bit 3) in DACR */
  55                MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IP;
  56                asm("nop");
  57
  58                /* Wait 30ns to allow banks to precharge */
  59                for (i = 0; i < 5; i++) {
  60                        asm ("nop");
  61                }
  62
  63                /* Write to this block to initiate precharge */
  64                *(u32 *)(CONFIG_SYS_SDRAM_BASE) = 0xA5A59696;
  65                asm("nop");
  66
  67                /* Set RE (bit 15) in DACR */
  68                MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_RE;
  69                asm("nop");
  70
  71                /* Wait for at least 8 auto refresh cycles to occur */
  72                for (i = 0; i < 2000; i++) {
  73                        asm(" nop");
  74                }
  75
  76                /* Finish the configuration by issuing the IMRS. */
  77                MCFSDRAMC_DACR0 |= MCFSDRAMC_DACR_IMRS;
  78                asm("nop");
  79
  80                /* Write to the SDRAM Mode Register */
  81                *(u32 *)(CONFIG_SYS_SDRAM_BASE + 0x400) = 0xA5A59696;
  82        }
  83        return dramsize;
  84}
  85