LXR uboot/board/freescale/mx31ads/mx31ads.c

   1/*
   2 * Copyright (C) 2008, Guennadi Liakhovetski <lg@denx.de>
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6
   7#include <common.h>
   8#include <netdev.h>
   9#include <asm/io.h>
  10#include <asm/arch/clock.h>
  11#include <asm/arch/imx-regs.h>
  12#include <asm/arch/sys_proto.h>
  13
  14DECLARE_GLOBAL_DATA_PTR;
  15
  16int dram_init(void)
  17{
  18        /* dram_init must store complete ramsize in gd->ram_size */
  19        gd->ram_size = get_ram_size((void *)PHYS_SDRAM_1,
  20                                PHYS_SDRAM_1_SIZE);
  21        return 0;
  22}
  23
  24int board_early_init_f(void)
  25{
  26        int i;
  27
  28        /* CS0: Nor Flash */
  29        /*
  30         * CS0L and CS0A values are from the RedBoot sources by Freescale
  31         * and are also equal to those used by Sascha Hauer for the Phytec
  32         * i.MX31 board. CS0U is just a slightly optimized hardware default:
  33         * the only non-zero field "Wait State Control" is set to half the
  34         * default value.
  35         */
  36        static const struct mxc_weimcs cs0 = {
  37                /*    sp wp bcd bcs psz pme sync dol cnc wsc ew wws edc */
  38                CSCR_U(0, 0,  0,  0,  0,  0,   0,  0,  0, 15, 0,  0,  0),
  39                /*   oea oen ebwa ebwn csa ebc dsz csn psr cre wrap csen */
  40                CSCR_L(1,  0,   0,   0,  0,  1,  5,  0,  0,  0,   1,   1),
  41                /*  ebra ebrn rwa rwn mum lah lbn lba dww dct wwu age cnc2 fce*/
  42                CSCR_A(0,   0,  7,  2,  0,  0,  2,  1,  0,  0,  0,  0,   0,   0)
  43        };
  44
  45        mxc_setup_weimcs(0, &cs0);
  46
  47        /* setup pins for UART1 */
  48        mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX);
  49        mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX);
  50        mx31_gpio_mux(MUX_RTS1__UART1_RTS_B);
  51        mx31_gpio_mux(MUX_CTS1__UART1_CTS_B);
  52
  53        /* SPI2 */
  54        mx31_gpio_mux(MUX_CSPI2_SS2__CSPI2_SS2_B);
  55        mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK);
  56        mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B);
  57        mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI);
  58        mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO);
  59        mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B);
  60        mx31_gpio_mux(MUX_CSPI2_SS1__CSPI2_SS1_B);
  61
  62        /* start SPI2 clock */
  63        __REG(CCM_CGR2) = __REG(CCM_CGR2) | (3 << 4);
  64
  65        /* PBC setup */
  66        /* Enable UART transceivers also reset the Ethernet/external UART */
  67        readw(CS4_BASE + 4);
  68
  69        writew(0x8023, CS4_BASE + 4);
  70
  71        /* RedBoot also has an empty loop with 100000 iterations here -
  72         * clock doesn't run yet */
  73        for (i = 0; i < 100000; i++)
  74                ;
  75
  76        /* Clear the reset, toggle the LEDs */
  77        writew(0xDF, CS4_BASE + 6);
  78
  79        /* clock still doesn't run */
  80        for (i = 0; i < 100000; i++)
  81                ;
  82
  83        /* See 1.5.4 in IMX31ADSE_PERI_BUS_CNTRL_CPLD_RM.pdf */
  84        readb(CS4_BASE + 8);
  85        readb(CS4_BASE + 7);
  86        readb(CS4_BASE + 8);
  87        readb(CS4_BASE + 7);
  88
  89        return 0;
  90}
  91
  92int board_init(void)
  93{
  94        gd->bd->bi_boot_params = 0x80000100;    /* adress of boot parameters */
  95
  96        return 0;
  97}
  98
  99int checkboard(void)
 100{
 101        printf("Board: MX31ADS\n");
 102        return 0;
 103}
 104
 105#ifdef CONFIG_CMD_NET
 106int board_eth_init(bd_t *bis)
 107{
 108        int rc = 0;
 109#ifdef CONFIG_CS8900
 110        rc = cs8900_initialize(0, CONFIG_CS8900_BASE);
 111#endif
 112        return rc;
 113}
 114#endif
 115