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14#include <common.h>
15#include <mpc5xxx.h>
16#include <pci.h>
17#include <asm/processor.h>
18#include <libfdt.h>
19#include <netdev.h>
20
21#ifdef CONFIG_VIDEO_SM501
22#include <sm501.h>
23#endif
24
25#if defined(CONFIG_MPC5200_DDR)
26#include "mt46v16m16-75.h"
27#else
28#include "mt48lc16m16a2-75.h"
29#endif
30
31#ifdef CONFIG_OF_LIBFDT
32#include <fdt_support.h>
33#endif
34
35DECLARE_GLOBAL_DATA_PTR;
36
37#ifdef CONFIG_PS2MULT
38void ps2mult_early_init(void);
39#endif
40
41#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) && \
42 defined(CONFIG_VIDEO)
43
44
45
46
47
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61
62
63static unsigned char edid_buf[128] = {
64 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00,
65 0x04, 0x21, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
66 0x01, 0x00, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00,
67 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
68 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x01, 0x01,
69 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
70 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x64, 0x00,
71 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
72 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
73 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00,
74 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
75 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x00, 0x00,
76 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
77 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10,
78 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
79 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x17,
80};
81#endif
82
83#ifndef CONFIG_SYS_RAMBOOT
84static void sdram_start (int hi_addr)
85{
86 long hi_addr_bit = hi_addr ? 0x01000000 : 0;
87
88
89 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000000 |
90 hi_addr_bit;
91 __asm__ volatile ("sync");
92
93
94 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
95 hi_addr_bit;
96 __asm__ volatile ("sync");
97
98#if SDRAM_DDR
99
100 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_EMODE;
101 __asm__ volatile ("sync");
102
103
104 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE | 0x04000000;
105 __asm__ volatile ("sync");
106#endif
107
108
109 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000002 |
110 hi_addr_bit;
111 __asm__ volatile ("sync");
112
113
114 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | 0x80000004 |
115 hi_addr_bit;
116 __asm__ volatile ("sync");
117
118
119 *(vu_long *)MPC5XXX_SDRAM_MODE = SDRAM_MODE;
120 __asm__ volatile ("sync");
121
122
123 *(vu_long *)MPC5XXX_SDRAM_CTRL = SDRAM_CONTROL | hi_addr_bit;
124 __asm__ volatile ("sync");
125}
126#endif
127
128
129
130
131
132
133
134phys_size_t initdram (int board_type)
135{
136 ulong dramsize = 0;
137 ulong dramsize2 = 0;
138 uint svr, pvr;
139
140#ifndef CONFIG_SYS_RAMBOOT
141 ulong test1, test2;
142
143
144 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x0000001c;
145 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = 0x40000000;
146 __asm__ volatile ("sync");
147
148
149 *(vu_long *)MPC5XXX_SDRAM_CONFIG1 = SDRAM_CONFIG1;
150 *(vu_long *)MPC5XXX_SDRAM_CONFIG2 = SDRAM_CONFIG2;
151 __asm__ volatile ("sync");
152
153#if SDRAM_DDR
154
155 *(vu_long *)MPC5XXX_CDM_PORCFG = SDRAM_TAPDELAY;
156 __asm__ volatile ("sync");
157#endif
158
159
160 sdram_start(0);
161 test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
162 sdram_start(1);
163 test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x20000000);
164 if (test1 > test2) {
165 sdram_start(0);
166 dramsize = test1;
167 } else {
168 dramsize = test2;
169 }
170
171
172 if (dramsize < (1 << 20)) {
173 dramsize = 0;
174 }
175
176
177 if (dramsize > 0) {
178 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0x13 +
179 __builtin_ffs(dramsize >> 20) - 1;
180 } else {
181 *(vu_long *)MPC5XXX_SDRAM_CS0CFG = 0;
182 }
183
184
185 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize + 0x0000001c;
186
187
188 if (!dramsize)
189 sdram_start(0);
190 test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
191 if (!dramsize) {
192 sdram_start(1);
193 test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x20000000);
194 }
195 if (test1 > test2) {
196 sdram_start(0);
197 dramsize2 = test1;
198 } else {
199 dramsize2 = test2;
200 }
201
202
203 if (dramsize2 < (1 << 20)) {
204 dramsize2 = 0;
205 }
206
207
208 if (dramsize2 > 0) {
209 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize
210 | (0x13 + __builtin_ffs(dramsize2 >> 20) - 1);
211 } else {
212 *(vu_long *)MPC5XXX_SDRAM_CS1CFG = dramsize;
213 }
214
215#else
216
217
218 dramsize = *(vu_long *)MPC5XXX_SDRAM_CS0CFG & 0xFF;
219 if (dramsize >= 0x13) {
220 dramsize = (1 << (dramsize - 0x13)) << 20;
221 } else {
222 dramsize = 0;
223 }
224
225
226 dramsize2 = *(vu_long *)MPC5XXX_SDRAM_CS1CFG & 0xFF;
227 if (dramsize2 >= 0x13) {
228 dramsize2 = (1 << (dramsize2 - 0x13)) << 20;
229 } else {
230 dramsize2 = 0;
231 }
232#endif
233
234
235
236
237
238
239
240
241
242
243 svr = get_svr();
244 pvr = get_pvr();
245 if ((SVR_MJREV(svr) >= 2) &&
246 (PVR_MAJ(pvr) == 1) && (PVR_MIN(pvr) == 4)) {
247
248 *(vu_long *)MPC5XXX_SDRAM_SDELAY = 0x04;
249 __asm__ volatile ("sync");
250 }
251
252#if defined(CONFIG_TQM5200_B)
253 return dramsize + dramsize2;
254#else
255 return dramsize;
256#endif
257}
258
259int checkboard (void)
260{
261#if defined(CONFIG_AEVFIFO)
262 puts ("Board: AEVFIFO\n");
263 return 0;
264#endif
265
266#if defined(CONFIG_TQM5200S)
267# define MODULE_NAME "TQM5200S"
268#else
269# define MODULE_NAME "TQM5200"
270#endif
271
272#if defined(CONFIG_STK52XX)
273# define CARRIER_NAME "STK52xx"
274#elif defined(CONFIG_TB5200)
275# define CARRIER_NAME "TB5200"
276#elif defined(CONFIG_CAM5200)
277# define CARRIER_NAME "CAM5200"
278#elif defined(CONFIG_FO300)
279# define CARRIER_NAME "FO300"
280#elif defined(CONFIG_CHARON)
281# define CARRIER_NAME "CHARON"
282#else
283# error "UNKNOWN"
284#endif
285
286 puts ( "Board: " MODULE_NAME " (TQ-Components GmbH)\n"
287 " on a " CARRIER_NAME " carrier board\n");
288
289 return 0;
290}
291
292#undef MODULE_NAME
293#undef CARRIER_NAME
294
295void flash_preinit(void)
296{
297
298
299
300
301
302
303 *(vu_long *)MPC5XXX_BOOTCS_CFG &= ~0x1;
304}
305
306
307#ifdef CONFIG_PCI
308static struct pci_controller hose;
309
310extern void pci_mpc5xxx_init(struct pci_controller *);
311
312void pci_init_board(void)
313{
314 pci_mpc5xxx_init(&hose);
315}
316#endif
317
318#if defined(CONFIG_CMD_IDE) && defined(CONFIG_IDE_RESET)
319
320#if defined (CONFIG_MINIFAP)
321#define SM501_POWER_MODE0_GATE 0x00000040UL
322#define SM501_POWER_MODE1_GATE 0x00000048UL
323#define POWER_MODE_GATE_GPIO_PWM_I2C 0x00000040UL
324#define SM501_GPIO_DATA_DIR_HIGH 0x0001000CUL
325#define SM501_GPIO_DATA_HIGH 0x00010004UL
326#define SM501_GPIO_51 0x00080000UL
327#endif
328
329void init_ide_reset (void)
330{
331 debug ("init_ide_reset\n");
332
333#if defined (CONFIG_MINIFAP)
334
335
336
337 *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE0_GATE) |=
338 POWER_MODE_GATE_GPIO_PWM_I2C;
339 *(vu_long *) (SM501_MMIO_BASE+SM501_POWER_MODE1_GATE) |=
340 POWER_MODE_GATE_GPIO_PWM_I2C;
341
342 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_DIR_HIGH) |=
343 SM501_GPIO_51;
344#else
345
346 *(vu_long *) MPC5XXX_WU_GPIO_ENABLE |= GPIO_PSC1_4;
347 *(vu_long *) MPC5XXX_WU_GPIO_DIR |= GPIO_PSC1_4;
348
349
350 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
351#endif
352}
353
354void ide_set_reset (int idereset)
355{
356 debug ("ide_reset(%d)\n", idereset);
357
358#if defined (CONFIG_MINIFAP)
359 if (idereset) {
360 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) &=
361 ~SM501_GPIO_51;
362 } else {
363 *(vu_long *) (SM501_MMIO_BASE+SM501_GPIO_DATA_HIGH) |=
364 SM501_GPIO_51;
365 }
366#else
367 if (idereset) {
368 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O &= ~GPIO_PSC1_4;
369 } else {
370 *(vu_long *) MPC5XXX_WU_GPIO_DATA_O |= GPIO_PSC1_4;
371 }
372#endif
373}
374#endif
375
376#ifdef CONFIG_POST
377
378
379
380
381int post_hotkeys_pressed(void)
382{
383#ifdef CONFIG_STK52XX
384 struct mpc5xxx_gpio *gpio;
385
386 gpio = (struct mpc5xxx_gpio*) MPC5XXX_GPIO;
387
388
389
390
391 gpio->port_config &= ~(0x00700000);
392
393
394 gpio->simple_gpioe |= 0x20000000;
395
396
397 gpio->simple_ddr &= ~(0x20000000);
398
399 return ((gpio->simple_ival & 0x20000000) ? 0 : 1);
400#else
401 return 0;
402#endif
403}
404#endif
405
406#ifdef CONFIG_BOARD_EARLY_INIT_R
407int board_early_init_r (void)
408{
409
410 extern int usb_cpu_init(void);
411
412#ifdef CONFIG_PS2MULT
413 ps2mult_early_init();
414#endif
415
416#if defined(CONFIG_USB_OHCI_NEW) && defined(CONFIG_SYS_USB_OHCI_CPU_INIT)
417
418 usb_cpu_init();
419#endif
420
421 return (0);
422}
423#endif
424
425#ifdef CONFIG_FO300
426int silent_boot (void)
427{
428 vu_long timer3_status;
429
430
431 *(vu_long *)MPC5XXX_GPT3_ENABLE = 0x00000004;
432
433
434 timer3_status = *(vu_long *)MPC5XXX_GPT3_STATUS;
435
436#ifdef FO300_SILENT_CONSOLE_WHEN_S1_CLOSED
437
438
439 if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 0)
440 return 1;
441#else
442
443
444 if (MPC5XXX_GPT_GPIO_PIN(timer3_status) == 1)
445 return 1;
446#endif
447
448 return 0;
449}
450
451int board_early_init_f (void)
452{
453 if (silent_boot())
454 gd->flags |= GD_FLG_SILENT;
455
456 return 0;
457}
458#endif
459
460#if defined(CONFIG_CHARON)
461#include <i2c.h>
462#include <asm/io.h>
463
464
465#define TFP410_REG_VEN_ID_L 0x00
466#define TFP410_REG_VEN_ID_H 0x01
467#define TFP410_REG_DEV_ID_L 0x02
468#define TFP410_REG_DEV_ID_H 0x03
469#define TFP410_REG_REV_ID 0x04
470
471#define TFP410_REG_CTL_1_MODE 0x08
472#define TFP410_REG_CTL_2_MODE 0x09
473#define TFP410_REG_CTL_3_MODE 0x0A
474
475#define TFP410_REG_CFG 0x0B
476
477#define TFP410_REG_DE_DLY 0x32
478#define TFP410_REG_DE_CTL 0x33
479#define TFP410_REG_DE_TOP 0x34
480#define TFP410_REG_DE_CNT_L 0x36
481#define TFP410_REG_DE_CNT_H 0x37
482#define TFP410_REG_DE_LIN_L 0x38
483#define TFP410_REG_DE_LIN_H 0x39
484
485#define TFP410_REG_H_RES_L 0x3A
486#define TFP410_REG_H_RES_H 0x3B
487#define TFP410_REG_V_RES_L 0x3C
488#define TFP410_REG_V_RES_H 0x3D
489
490static int tfp410_read_reg(int reg, uchar *buf)
491{
492 if (i2c_read(CONFIG_SYS_TFP410_ADDR, reg, 1, buf, 1) != 0) {
493 puts ("Error reading the chip.\n");
494 return 1;
495 }
496 return 0;
497}
498
499static int tfp410_write_reg(int reg, uchar buf)
500{
501 if (i2c_write(CONFIG_SYS_TFP410_ADDR, reg, 1, &buf, 1) != 0) {
502 puts ("Error writing the chip.\n");
503 return 1;
504 }
505 return 0;
506}
507
508typedef struct _tfp410_config {
509 int reg;
510 uchar val;
511}TFP410_CONFIG;
512
513static TFP410_CONFIG tfp410_configtbl[] = {
514 {TFP410_REG_CTL_1_MODE, 0x37},
515 {TFP410_REG_CTL_2_MODE, 0x20},
516 {TFP410_REG_CTL_3_MODE, 0x80},
517 {TFP410_REG_DE_DLY, 0x90},
518 {TFP410_REG_DE_CTL, 0x00},
519 {TFP410_REG_DE_TOP, 0x23},
520 {TFP410_REG_DE_CNT_H, 0x02},
521 {TFP410_REG_DE_CNT_L, 0x80},
522 {TFP410_REG_DE_LIN_H, 0x01},
523 {TFP410_REG_DE_LIN_L, 0xe0},
524 {-1, 0},
525};
526
527static int charon_last_stage_init(void)
528{
529 volatile struct mpc5xxx_lpb *lpb =
530 (struct mpc5xxx_lpb *) MPC5XXX_LPB;
531 int oldbus = i2c_get_bus_num();
532 uchar buf;
533 int i = 0;
534
535 i2c_set_bus_num(CONFIG_SYS_TFP410_BUS);
536
537
538 if (tfp410_read_reg(TFP410_REG_DEV_ID_H, &buf) != 0)
539 return -1;
540 if (!(buf & 0x04))
541 return -1;
542 if (tfp410_read_reg(TFP410_REG_DEV_ID_L, &buf) != 0)
543 return -1;
544 if (!(buf & 0x10))
545 return -1;
546
547 while (tfp410_configtbl[i].reg != -1) {
548 int ret;
549
550 ret = tfp410_write_reg(tfp410_configtbl[i].reg,
551 tfp410_configtbl[i].val);
552 if (ret != 0)
553 return -1;
554 i++;
555 }
556 printf("TFP410 initialized.\n");
557 i2c_set_bus_num(oldbus);
558
559
560 setbits_be32(&lpb->cs_deadcycle, 0xffffcfff);
561 return 0;
562}
563#endif
564
565int last_stage_init (void)
566{
567
568
569
570
571 u16 save, tmp;
572 int restore;
573
574
575
576
577
578
579 save = *(volatile u16 *)CONFIG_SYS_CS2_START;
580 restore = 1;
581
582
583 *(volatile u16 *)CONFIG_SYS_CS2_START = 0xA5A5;
584 __asm__ volatile ("sync");
585
586
587
588
589 tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
590 if (tmp == 0xA5A5)
591 puts ("!! possible error in SRAM detection\n");
592
593 if (*(volatile u16 *)CONFIG_SYS_CS2_START != 0xA5A5) {
594
595 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 18);
596 *(vu_long *)MPC5XXX_CS2_START = 0x0000FFFF;
597 *(vu_long *)MPC5XXX_CS2_STOP = 0x0000FFFF;
598 restore = 0;
599 __asm__ volatile ("sync");
600 } else if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0xA5A5) {
601
602 *(volatile u16 *)CONFIG_SYS_CS2_START = 0x1111;
603 __asm__ volatile ("sync");
604 if (*(volatile u16 *)(CONFIG_SYS_CS2_START + (1<<19)) == 0x1111) {
605
606 *(vu_long *)MPC5XXX_CS2_STOP = STOP_REG(CONFIG_SYS_CS2_START,
607 0x80000);
608 __asm__ volatile ("sync");
609 puts ("SRAM: 512 kB\n");
610 }
611 else
612 puts ("!! possible error in SRAM detection\n");
613 } else {
614 puts ("SRAM: 1 MB\n");
615 }
616
617 if (restore) {
618 *(volatile u16 *)CONFIG_SYS_CS2_START = save;
619 __asm__ volatile ("sync");
620 }
621
622#ifndef CONFIG_TQM5200S
623
624
625
626
627
628 save = *(volatile u16 *)CONFIG_SYS_CS1_START;
629 restore = 1;
630
631
632 *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
633 __asm__ volatile ("sync");
634
635
636
637
638 tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
639 if (tmp == 0xA5A5)
640 puts ("!! possible error in grafic controller detection\n");
641
642 if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
643
644 *(vu_long *)MPC5XXX_ADDECR &= ~(1 << 17);
645 *(vu_long *)MPC5XXX_CS1_START = 0x0000FFFF;
646 *(vu_long *)MPC5XXX_CS1_STOP = 0x0000FFFF;
647 restore = 0;
648 __asm__ volatile ("sync");
649 } else {
650 puts ("VGA: SMI501 (Voyager) with 8 MB\n");
651 }
652
653 if (restore) {
654 *(volatile u16 *)CONFIG_SYS_CS1_START = save;
655 __asm__ volatile ("sync");
656 }
657
658#ifdef CONFIG_FO300
659 if (silent_boot()) {
660 setenv("bootdelay", "0");
661 disable_ctrlc(1);
662 }
663#endif
664#endif
665
666#if defined(CONFIG_CHARON)
667 charon_last_stage_init();
668#endif
669 return 0;
670}
671
672#ifdef CONFIG_VIDEO_SM501
673
674#ifdef CONFIG_FO300
675#define DISPLAY_WIDTH 800
676#else
677#define DISPLAY_WIDTH 640
678#endif
679#define DISPLAY_HEIGHT 480
680
681#ifdef CONFIG_VIDEO_SM501_8BPP
682#error CONFIG_VIDEO_SM501_8BPP not supported.
683#endif
684
685#ifdef CONFIG_VIDEO_SM501_16BPP
686#error CONFIG_VIDEO_SM501_16BPP not supported.
687#endif
688#ifdef CONFIG_VIDEO_SM501_32BPP
689static const SMI_REGS init_regs [] =
690{
691#if 0
692 {0x00004, 0x0},
693 {0x00048, 0x00021807},
694 {0x0004C, 0x10090a01},
695 {0x00054, 0x1},
696 {0x00040, 0x00021807},
697 {0x00044, 0x10090a01},
698 {0x00054, 0x0},
699 {0x80200, 0x00010000},
700 {0x80204, 0x0},
701 {0x80208, 0x0A000A00},
702 {0x8020C, 0x02fa027f},
703 {0x80210, 0x004a028b},
704 {0x80214, 0x020c01df},
705 {0x80218, 0x000201e9},
706 {0x80200, 0x00013306},
707#else
708#ifdef CONFIG_FO300
709 {0x00004, 0x0},
710 {0x00048, 0x00021807},
711 {0x0004C, 0x301a0a01},
712 {0x00054, 0x1},
713 {0x00040, 0x00021807},
714 {0x00044, 0x091a0a01},
715 {0x00054, 0x0},
716 {0x80000, 0x0f013106},
717 {0x80004, 0xc428bb17},
718 {0x8000C, 0x00000000},
719 {0x80010, 0x0C800C80},
720 {0x80014, 0x03200000},
721 {0x80018, 0x01e00000},
722 {0x8001C, 0x00000000},
723 {0x80020, 0x01e00320},
724 {0x80024, 0x042a031f},
725 {0x80028, 0x0086034a},
726 {0x8002C, 0x020c01df},
727 {0x80030, 0x000201ea},
728 {0x80200, 0x00010000},
729#else
730 {0x00004, 0x0},
731 {0x00048, 0x00021807},
732 {0x0004C, 0x091a0a01},
733 {0x00054, 0x1},
734 {0x00040, 0x00021807},
735 {0x00044, 0x091a0a01},
736 {0x00054, 0x0},
737 {0x80000, 0x0f013106},
738 {0x80004, 0xc428bb17},
739 {0x8000C, 0x00000000},
740 {0x80010, 0x0a000a00},
741 {0x80014, 0x02800000},
742 {0x80018, 0x01e00000},
743 {0x8001C, 0x00000000},
744 {0x80020, 0x01e00280},
745 {0x80024, 0x02fa027f},
746 {0x80028, 0x004a028b},
747 {0x8002C, 0x020c01df},
748 {0x80030, 0x000201e9},
749 {0x80200, 0x00010000},
750#endif
751#endif
752 {0, 0}
753};
754#endif
755
756#ifdef CONFIG_CONSOLE_EXTRA_INFO
757
758
759
760void video_get_info_str (int line_number, char *info)
761{
762 if (line_number == 1) {
763 strcpy (info, " Board: TQM5200 (TQ-Components GmbH)");
764#if defined (CONFIG_CHARON) || defined (CONFIG_FO300) || \
765 defined(CONFIG_STK52XX) || defined(CONFIG_TB5200)
766 } else if (line_number == 2) {
767#if defined (CONFIG_CHARON)
768 strcpy (info, " on a CHARON carrier board");
769#endif
770#if defined (CONFIG_STK52XX)
771 strcpy (info, " on a STK52xx carrier board");
772#endif
773#if defined (CONFIG_TB5200)
774 strcpy (info, " on a TB5200 carrier board");
775#endif
776#if defined (CONFIG_FO300)
777 strcpy (info, " on a FO300 carrier board");
778#endif
779#endif
780 }
781 else {
782 info [0] = '\0';
783 }
784}
785#endif
786
787
788
789
790
791unsigned int board_video_init (void)
792{
793 u16 save, tmp;
794 int restore, ret;
795
796
797
798
799
800
801 save = *(volatile u16 *)CONFIG_SYS_CS1_START;
802 restore = 1;
803
804
805 *(volatile u16 *)CONFIG_SYS_CS1_START = 0xA5A5;
806 __asm__ volatile ("sync");
807
808
809
810
811 tmp = *(volatile u16 *)CONFIG_SYS_FLASH_BASE;
812 if (tmp == 0xA5A5)
813 puts ("!! possible error in grafic controller detection\n");
814
815 if (*(volatile u16 *)CONFIG_SYS_CS1_START != 0xA5A5) {
816
817 restore = 0;
818 ret = 0;
819 } else {
820 ret = SM501_MMIO_BASE;
821 }
822
823 if (restore) {
824 *(volatile u16 *)CONFIG_SYS_CS1_START = save;
825 __asm__ volatile ("sync");
826 }
827 return ret;
828}
829
830
831
832
833unsigned int board_video_get_fb (void)
834{
835 return SM501_FB_BASE;
836}
837
838
839
840
841void board_validate_screen (unsigned int base)
842{
843}
844
845
846
847
848const SMI_REGS *board_get_regs (void)
849{
850 return init_regs;
851}
852
853int board_get_width (void)
854{
855 return DISPLAY_WIDTH;
856}
857
858int board_get_height (void)
859{
860 return DISPLAY_HEIGHT;
861}
862
863#endif
864
865#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
866int ft_board_setup(void *blob, bd_t *bd)
867{
868 ft_cpu_setup(blob, bd);
869#if defined(CONFIG_VIDEO)
870 fdt_add_edid(blob, "smi,sm501", edid_buf);
871#endif
872
873 return 0;
874}
875#endif
876
877#if defined(CONFIG_RESET_PHY_R)
878#include <miiphy.h>
879
880void reset_phy(void)
881{
882
883 miiphy_write("FEC", CONFIG_PHY_ADDR, 0x01, 0x09);
884}
885#endif
886
887int board_eth_init(bd_t *bis)
888{
889 cpu_eth_init(bis);
890 return pci_eth_init(bis);
891}
892