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12#ifndef __CONFIG_H
13#define __CONFIG_H
14
15
16
17
18
19
20#define CONFIG_405EP 1
21#define CONFIG_VOM405 1
22
23#define CONFIG_SYS_TEXT_BASE 0xFFFC8000
24
25#define CONFIG_BOARD_EARLY_INIT_F 1
26#define CONFIG_MISC_INIT_R 1
27
28#define CONFIG_SYS_CLK_FREQ 33330000
29
30#define CONFIG_BAUDRATE 9600
31#define CONFIG_BOOTDELAY 3
32
33#undef CONFIG_BOOTARGS
34#undef CONFIG_BOOTCOMMAND
35
36#define CONFIG_PREBOOT
37
38#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
39
40#define CONFIG_PPC4xx_EMAC
41#undef CONFIG_HAS_ETH1
42
43#define CONFIG_MII 1
44#define CONFIG_PHY_ADDR 0
45#define CONFIG_LXT971_NO_SLEEP 1
46#define CONFIG_RESET_PHY_R 1
47
48
49
50
51#define CONFIG_BOOTP_SUBNETMASK
52#define CONFIG_BOOTP_GATEWAY
53#define CONFIG_BOOTP_HOSTNAME
54#define CONFIG_BOOTP_BOOTPATH
55#define CONFIG_BOOTP_DNS
56#define CONFIG_BOOTP_DNS2
57#define CONFIG_BOOTP_SEND_HOSTNAME
58
59
60
61
62
63#include <config_cmd_default.h>
64
65#define CONFIG_CMD_DHCP
66#define CONFIG_CMD_BSP
67#define CONFIG_CMD_ELF
68#define CONFIG_CMD_NAND
69#define CONFIG_CMD_I2C
70#define CONFIG_CMD_DATE
71#define CONFIG_CMD_MII
72#define CONFIG_CMD_PING
73#define CONFIG_CMD_EEPROM
74
75
76#undef CONFIG_WATCHDOG
77
78#define CONFIG_SDRAM_BANK0 1
79
80#undef CONFIG_PRAM
81
82
83
84
85#define CONFIG_SYS_LONGHELP
86
87#undef CONFIG_SYS_HUSH_PARSER
88
89#if defined(CONFIG_CMD_KGDB)
90#define CONFIG_SYS_CBSIZE 1024
91#else
92#define CONFIG_SYS_CBSIZE 256
93#endif
94#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
95#define CONFIG_SYS_MAXARGS 16
96#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
97
98#define CONFIG_SYS_DEVICE_NULLDEV 1
99
100#define CONFIG_SYS_CONSOLE_INFO_QUIET 1
101
102#define CONFIG_SYS_MEMTEST_START 0x0400000
103#define CONFIG_SYS_MEMTEST_END 0x0C00000
104
105#define CONFIG_CONS_INDEX 2
106#define CONFIG_SYS_NS16550
107#define CONFIG_SYS_NS16550_SERIAL
108#define CONFIG_SYS_NS16550_REG_SIZE 1
109#define CONFIG_SYS_NS16550_CLK get_serial_clock()
110
111#undef CONFIG_SYS_EXT_SERIAL_CLOCK
112#define CONFIG_SYS_BASE_BAUD 691200
113
114
115#define CONFIG_SYS_BAUDRATE_TABLE \
116 { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
117 57600, 115200, 230400, 460800, 921600 }
118
119#define CONFIG_SYS_LOAD_ADDR 0x100000
120#define CONFIG_SYS_EXTBDINFO 1
121
122#define CONFIG_ZERO_BOOTDELAY_CHECK
123
124#define CONFIG_VERSION_VARIABLE 1
125
126#define CONFIG_SYS_RX_ETH_BUFFER 16
127
128
129
130
131
132#define CONFIG_RTC_DS1337
133#define CONFIG_SYS_I2C_RTC_ADDR 0x68
134
135
136
137
138
139#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
140#define CONFIG_SYS_MAX_NAND_DEVICE 1
141#define NAND_BIG_DELAY_US 25
142
143#define CONFIG_SYS_NAND_CE (0x80000000 >> 1)
144#define CONFIG_SYS_NAND_RDY (0x80000000 >> 4)
145#define CONFIG_SYS_NAND_CLE (0x80000000 >> 2)
146#define CONFIG_SYS_NAND_ALE (0x80000000 >> 3)
147
148#define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1
149#define CONFIG_SYS_NAND_QUIET 1
150
151#define CONFIG_SYS_NAND_MAX_OOBFREE 2
152#define CONFIG_SYS_NAND_MAX_ECCPOS 48
153
154
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157
158
159#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
160
161
162
163#define FLASH_BASE0_PRELIM 0xFFC00000
164
165#define CONFIG_SYS_MAX_FLASH_BANKS 1
166#define CONFIG_SYS_MAX_FLASH_SECT 256
167
168#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
169#define CONFIG_SYS_FLASH_WRITE_TOUT 1000
170
171#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
172#define CONFIG_SYS_FLASH_ADDR0 0x5555
173#define CONFIG_SYS_FLASH_ADDR1 0x2AAA
174
175
176
177
178#define CONFIG_SYS_FLASH_READ0 0x0000
179#define CONFIG_SYS_FLASH_READ1 0x0001
180#define CONFIG_SYS_FLASH_READ2 0x0002
181
182#define CONFIG_SYS_FLASH_EMPTY_INFO
183
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187
188
189#define CONFIG_SYS_SDRAM_BASE 0x00000000
190#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE
191#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
192#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1)
193#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
194
195#if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM)
196# define CONFIG_SYS_RAMBOOT 1
197#else
198# undef CONFIG_SYS_RAMBOOT
199#endif
200
201
202
203
204#define CONFIG_ENV_IS_IN_EEPROM 1
205#define CONFIG_ENV_OFFSET 0x100
206#define CONFIG_ENV_SIZE 0x700
207
208
209
210
211
212#define CONFIG_SYS_I2C
213#define CONFIG_SYS_I2C_PPC4XX
214#define CONFIG_SYS_I2C_PPC4XX_CH0
215#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
216#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F
217
218#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
219#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
220
221#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
222#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
223
224
225#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
226
227#define CONFIG_SYS_EEPROM_WREN 1
228
229
230
231
232#define CONFIG_SYS_PLD_BASE 0xf0000000
233#define CONFIG_SYS_NAND_BASE 0xF4000000
234
235
236#define CONFIG_SYS_EBC_PB0AP 0x92015480
237#define CONFIG_SYS_EBC_PB0CR 0xFFC5A000
238
239
240#define CONFIG_SYS_EBC_PB1AP 0x92015480
241#define CONFIG_SYS_EBC_PB1CR 0xF4018000
242
243
244#define CONFIG_SYS_EBC_PB2AP 0x010053C0
245#define CONFIG_SYS_EBC_PB2CR 0xF0018000
246
247
248
249
250#define CONFIG_SYS_XSVF_DEFAULT_ADDR 0xfffc0000
251
252
253#define CONFIG_SYS_FPGA_PRG 0x04000000
254#define CONFIG_SYS_FPGA_CLK 0x02000000
255#define CONFIG_SYS_FPGA_DATA 0x01000000
256#define CONFIG_SYS_FPGA_INIT 0x00010000
257#define CONFIG_SYS_FPGA_DONE 0x00008000
258
259
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262
263#define CONFIG_SYS_TEMP_STACK_OCM 1
264
265
266#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
267#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
268#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
269#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
270
271#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
272#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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289
290#define CONFIG_SYS_GPIO0_OSRL 0x40000500
291#define CONFIG_SYS_GPIO0_OSRH 0x00000110
292#define CONFIG_SYS_GPIO0_ISR1L 0x00000000
293#define CONFIG_SYS_GPIO0_ISR1H 0x14000045
294#define CONFIG_SYS_GPIO0_TSRL 0x00000000
295#define CONFIG_SYS_GPIO0_TSRH 0x00000000
296#define CONFIG_SYS_GPIO0_TCR 0xF7FE0014
297
298#define CONFIG_SYS_EEPROM_WP (0x80000000 >> 8)
299#define CONFIG_SYS_PLD_RESET (0x80000000 >> 12)
300
301
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303
304
305#define PLLMR0_DEFAULT PLLMR0_133_66_66_33
306#define PLLMR1_DEFAULT PLLMR1_133_66_66_33
307
308#endif
309