LXR uboot/include/configs/CPCI2DP.h

   1/*
   2 * (C) Copyright 2005
   3 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 */
   7
   8/*
   9 * board/config.h - configuration options, board specific
  10 */
  11
  12#ifndef __CONFIG_H
  13#define __CONFIG_H
  14
  15/*
  16 * High Level Configuration Options
  17 * (easy to change)
  18 */
  19
  20#define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  21
  22#define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  23
  24#define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  25
  26#define CONFIG_SYS_CLK_FREQ     33330000 /* external frequency to pll   */
  27
  28#define CONFIG_BAUDRATE         9600
  29#define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  30
  31#undef  CONFIG_BOOTARGS
  32#undef  CONFIG_BOOTCOMMAND
  33
  34#define CONFIG_PREBOOT                  /* enable preboot variable      */
  35
  36#define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  37#define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  38
  39#define CONFIG_MII              1       /* MII PHY management           */
  40#define CONFIG_PHY_ADDR         0       /* PHY address                  */
  41
  42/*
  43 * BOOTP options
  44 */
  45#define CONFIG_BOOTP_BOOTFILESIZE
  46#define CONFIG_BOOTP_BOOTPATH
  47#define CONFIG_BOOTP_GATEWAY
  48#define CONFIG_BOOTP_HOSTNAME
  49
  50
  51/*
  52 * Command line configuration.
  53 */
  54#include <config_cmd_default.h>
  55
  56#define CONFIG_CMD_PCI
  57#define CONFIG_CMD_IRQ
  58#define CONFIG_CMD_ELF
  59#define CONFIG_CMD_I2C
  60#define CONFIG_CMD_BSP
  61#define CONFIG_CMD_EEPROM
  62
  63#undef CONFIG_CMD_NET
  64#undef CONFIG_CMD_NFS
  65
  66#undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  67
  68#define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
  69
  70/*
  71 * Miscellaneous configurable options
  72 */
  73#define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  74
  75#undef  CONFIG_SYS_HUSH_PARSER                  /* use "hush" command parser    */
  76
  77#if defined(CONFIG_CMD_KGDB)
  78#define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
  79#else
  80#define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
  81#endif
  82#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  83#define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
  84#define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  85
  86#define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device       */
  87
  88#define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console @ startup*/
  89
  90#define CONFIG_AUTO_COMPLETE    1       /* add autocompletion support   */
  91
  92#define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
  93#define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
  94
  95#define CONFIG_CONS_INDEX       2       /* Use UART1                    */
  96#define CONFIG_SYS_NS16550
  97#define CONFIG_SYS_NS16550_SERIAL
  98#define CONFIG_SYS_NS16550_REG_SIZE     1
  99#define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 100
 101#undef  CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
 102#define CONFIG_SYS_BASE_BAUD        691200
 103
 104/* The following table includes the supported baudrates */
 105#define CONFIG_SYS_BAUDRATE_TABLE       \
 106        { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 107         57600, 115200, 230400, 460800, 921600 }
 108
 109#define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 110#define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 111
 112#define CONFIG_LOOPW            1       /* enable loopw command         */
 113
 114#define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 115
 116#define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 117
 118#define CONFIG_SYS_RX_ETH_BUFFER        16      /* use 16 rx buffer on 405 emac */
 119
 120/*-----------------------------------------------------------------------
 121 * PCI stuff
 122 *-----------------------------------------------------------------------
 123 */
 124#define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 125#define PCI_HOST_FORCE  1               /* configure as pci host        */
 126#define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 127
 128#define CONFIG_PCI                      /* include pci support          */
 129#define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 130#define CONFIG_PCI_HOST PCI_HOST_AUTO   /* select pci host function     */
 131#define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 132                                        /* resource configuration       */
 133
 134#define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 135
 136#define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
 137
 138#define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
 139
 140#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
 141#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x040b  /* PCI Device ID: CPCI-2DP      */
 142#define CONFIG_SYS_PCI_CLASSCODE       0x0280   /* PCI Class Code: Network/Other*/
 143
 144#define CONFIG_SYS_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
 145#define CONFIG_SYS_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
 146#define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 147#define CONFIG_SYS_PCI_PTM2LA   0xef000000      /* point to internal regs + PB0/1 */
 148#define CONFIG_SYS_PCI_PTM2MS  0xff000001      /* 16MB, enable                  */
 149#define CONFIG_SYS_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
 150
 151/*-----------------------------------------------------------------------
 152 * Start addresses for the final memory configuration
 153 * (Set up by the startup code)
 154 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 155 */
 156#define CONFIG_SYS_SDRAM_BASE           0x00000000
 157#define CONFIG_SYS_FLASH_BASE           0xFFFC0000
 158#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 159#define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Monitor   */
 160#define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserve 128 kB for malloc()  */
 161
 162/*
 163 * For booting Linux, the board info and command line data
 164 * have to be in the first 8 MB of memory, since this is
 165 * the maximum mapped by the Linux kernel during initialization.
 166 */
 167#define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 168/*-----------------------------------------------------------------------
 169 * FLASH organization
 170 */
 171#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 172#define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 173
 174#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 175#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 176
 177#define CONFIG_SYS_FLASH_WORD_SIZE      unsigned short  /* flash word size (width)      */
 178#define CONFIG_SYS_FLASH_ADDR0          0x5555  /* 1st address for flash config cycles  */
 179#define CONFIG_SYS_FLASH_ADDR1          0x2AAA  /* 2nd address for flash config cycles  */
 180
 181#define CONFIG_SYS_FLASH_READ0          0x0000  /* 0 is standard                        */
 182#define CONFIG_SYS_FLASH_READ1          0x0001  /* 1 is standard                        */
 183#define CONFIG_SYS_FLASH_READ2          0x0002  /* 2 is standard                        */
 184
 185#define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 186
 187#define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 188#define CONFIG_ENV_OFFSET               0x000   /* environment starts at the beginning of the EEPROM */
 189#define CONFIG_ENV_SIZE         0x400   /* 1024 bytes may be used for env vars */
 190
 191/*-----------------------------------------------------------------------
 192 * I2C EEPROM (CAT24WC16) for environment
 193 */
 194#define CONFIG_SYS_I2C
 195#define CONFIG_SYS_I2C_PPC4XX
 196#define CONFIG_SYS_I2C_PPC4XX_CH0
 197#define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 198#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 199
 200#define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT28WC08             */
 201#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address             */
 202/* mask of address bits that overflow into the "EEPROM chip address"    */
 203#define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 204#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24WC08 has   */
 205                                        /* 16 byte page write mode using*/
 206                                        /* last 4 bits of the address   */
 207#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 208
 209#define CONFIG_SYS_EEPROM_WREN         1
 210
 211/*
 212 * Init Memory Controller:
 213 *
 214 * BR0/1 and OR0/1 (FLASH)
 215 */
 216#define FLASH_BASE0_PRELIM      0xFFE00000      /* FLASH bank #0        */
 217#define FLASH_BASE1_PRELIM      0               /* FLASH bank #1        */
 218
 219/*-----------------------------------------------------------------------
 220 * External Bus Controller (EBC) Setup
 221 */
 222
 223/* Memory Bank 0 (Flash Bank 0) initialization                                  */
 224#define CONFIG_SYS_EBC_PB0AP            0x92015480
 225#define CONFIG_SYS_EBC_PB0CR            0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 226
 227/* Memory Bank 2 (PB0) initialization                                   */
 228#define CONFIG_SYS_EBC_PB2AP            0x03004580  /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
 229#define CONFIG_SYS_EBC_PB2CR            0xEF018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 230
 231/* Memory Bank 3 (PB1) initialization                           */
 232#define CONFIG_SYS_EBC_PB3AP            0x03004580  /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
 233#define CONFIG_SYS_EBC_PB3CR            0xEF118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
 234
 235/*-----------------------------------------------------------------------
 236 * Definitions for initial stack pointer and data area (in data cache)
 237 */
 238#define CONFIG_SYS_INIT_DCACHE_CS       7       /* use cs # 7 for data cache memory    */
 239
 240#define CONFIG_SYS_INIT_RAM_ADDR        0x40000000  /* use data cache                  */
 241#define CONFIG_SYS_INIT_RAM_SIZE        0x2000  /* Size of used area in RAM            */
 242#define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 243#define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 244
 245/*-----------------------------------------------------------------------
 246 * GPIO definitions
 247 */
 248#define CONFIG_SYS_EEPROM_WP            (0x80000000 >> 13)   /* GPIO13 */
 249#define CONFIG_SYS_SELF_RST             (0x80000000 >> 14)   /* GPIO14 */
 250#define CONFIG_SYS_PB_LED               (0x80000000 >> 16)   /* GPIO16 */
 251#define CONFIG_SYS_INTA_FAKE            (0x80000000 >> 23)   /* GPIO23 */
 252
 253#endif  /* __CONFIG_H */
 254