1/* 2 * Configuation settings for the Freescale MCF52277 EVB board. 3 * 4 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. 5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com) 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10/* 11 * board/config.h - configuration options, board specific 12 */ 13 14#ifndef _M52277EVB_H 15#define _M52277EVB_H 16 17/* 18 * High Level Configuration Options 19 * (easy to change) 20 */ 21#define CONFIG_MCF5227x /* define processor family */ 22#define CONFIG_M52277 /* define processor type */ 23#define CONFIG_M52277EVB /* M52277EVB board */ 24 25#define CONFIG_MCFUART 26#define CONFIG_SYS_UART_PORT (0) 27#define CONFIG_BAUDRATE 115200 28 29#undef CONFIG_WATCHDOG 30 31#define CONFIG_TIMESTAMP /* Print image info with timestamp */ 32 33/* 34 * BOOTP options 35 */ 36#define CONFIG_BOOTP_BOOTFILESIZE 37#define CONFIG_BOOTP_BOOTPATH 38#define CONFIG_BOOTP_GATEWAY 39#define CONFIG_BOOTP_HOSTNAME 40 41/* Command line configuration */ 42#include <config_cmd_default.h> 43 44#define CONFIG_CMD_CACHE 45#define CONFIG_CMD_DATE 46#define CONFIG_CMD_ELF 47#define CONFIG_CMD_FLASH 48#define CONFIG_CMD_I2C 49#define CONFIG_CMD_JFFS2 50#define CONFIG_CMD_LOADB 51#define CONFIG_CMD_LOADS 52#define CONFIG_CMD_MEMORY 53#define CONFIG_CMD_MISC 54#undef CONFIG_CMD_NET 55#undef CONFIG_CMD_NFS 56#define CONFIG_CMD_REGINFO 57#undef CONFIG_CMD_USB 58#undef CONFIG_CMD_BMP 59#define CONFIG_CMD_SPI 60#define CONFIG_CMD_SF 61 62#define CONFIG_HOSTNAME M52277EVB 63#define CONFIG_SYS_UBOOT_END 0x3FFFF 64#define CONFIG_SYS_LOAD_ADDR2 0x40010007 65#ifdef CONFIG_SYS_STMICRO_BOOT 66/* ST Micro serial flash */ 67#define CONFIG_EXTRA_ENV_SETTINGS \ 68 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 69 "loadaddr=0x40010000\0" \ 70 "uboot=u-boot.bin\0" \ 71 "load=loadb ${loadaddr} ${baudrate};" \ 72 "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ 73 "upd=run load; run prog\0" \ 74 "prog=sf probe 0:2 10000 1;" \ 75 "sf erase 0 30000;" \ 76 "sf write ${loadaddr} 0 30000;" \ 77 "save\0" \ 78 "" 79#endif 80#ifdef CONFIG_SYS_SPANSION_BOOT 81#define CONFIG_EXTRA_ENV_SETTINGS \ 82 "inpclk=" __stringify(CONFIG_SYS_INPUT_CLKSRC) "\0" \ 83 "loadaddr=0x40010000\0" \ 84 "uboot=u-boot.bin\0" \ 85 "load=loadb ${loadaddr} ${baudrate}\0" \ 86 "upd=run load; run prog\0" \ 87 "prog=prot off " __stringify(CONFIG_SYS_FLASH_BASE) \ 88 " " __stringify(CONFIG_SYS_UBOOT_END) ";" \ 89 "era " __stringify(CONFIG_SYS_FLASH_BASE) " " \ 90 __stringify(CONFIG_SYS_UBOOT_END) ";" \ 91 "cp.b ${loadaddr} " __stringify(CONFIG_SYS_FLASH_BASE) \ 92 " ${filesize}; save\0" \ 93 "updsbf=run loadsbf; run progsbf\0" \ 94 "loadsbf=loadb ${loadaddr} ${baudrate};" \ 95 "loadb " __stringify(CONFIG_SYS_LOAD_ADDR2) " ${baudrate} \0" \ 96 "progsbf=sf probe 0:2 10000 1;" \ 97 "sf erase 0 30000;" \ 98 "sf write ${loadaddr} 0 30000;" \ 99 "" 100#endif 101 102#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */ 103/* LCD */ 104#ifdef CONFIG_CMD_BMP 105#define CONFIG_LCD 106#define CONFIG_SPLASH_SCREEN 107#define CONFIG_LCD_LOGO 108#define CONFIG_SHARP_LQ035Q7DH06 109#endif 110 111/* USB */ 112#ifdef CONFIG_CMD_USB 113#define CONFIG_USB_EHCI 114#define CONFIG_USB_STORAGE 115#define CONFIG_DOS_PARTITION 116#define CONFIG_MAC_PARTITION 117#define CONFIG_ISO_PARTITION 118#define CONFIG_SYS_USB_EHCI_REGS_BASE 0xFC0B0000 119#define CONFIG_SYS_USB_EHCI_CPU_INIT 120#endif 121 122/* Realtime clock */ 123#define CONFIG_MCFRTC 124#undef RTC_DEBUG 125#define CONFIG_SYS_RTC_OSCILLATOR (32 * CONFIG_SYS_HZ) 126 127/* Timer */ 128#define CONFIG_MCFTMR 129#undef CONFIG_MCFPIT 130 131/* I2c */ 132#define CONFIG_SYS_I2C 133#define CONFIG_SYS_I2C_FSL 134#define CONFIG_SYS_FSL_I2C_SPEED 80000 135#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F 136#define CONFIG_SYS_FSL_I2C_OFFSET 0x58000 137#define CONFIG_SYS_IMMR CONFIG_SYS_MBAR 138 139/* DSPI and Serial Flash */ 140#define CONFIG_CF_SPI 141#define CONFIG_CF_DSPI 142#define CONFIG_HARD_SPI 143#define CONFIG_SYS_SBFHDR_SIZE 0x7 144#ifdef CONFIG_CMD_SPI 145# define CONFIG_SYS_DSPI_CS2 146# define CONFIG_SPI_FLASH 147# define CONFIG_SPI_FLASH_STMICRO 148 149# define CONFIG_SYS_DSPI_CTAR0 (DSPI_CTAR_TRSZ(7) | \ 150 DSPI_CTAR_PCSSCK_1CLK | \ 151 DSPI_CTAR_PASC(0) | \ 152 DSPI_CTAR_PDT(0) | \ 153 DSPI_CTAR_CSSCK(0) | \ 154 DSPI_CTAR_ASC(0) | \ 155 DSPI_CTAR_DT(1)) 156#endif 157 158/* Input, PCI, Flexbus, and VCO */ 159#define CONFIG_EXTRA_CLOCK 160 161#define CONFIG_SYS_INPUT_CLKSRC 16000000 162 163#define CONFIG_PRAM 2048 /* 2048 KB */ 164 165#define CONFIG_SYS_PROMPT "-> " 166#define CONFIG_SYS_LONGHELP /* undef to save memory */ 167 168#if defined(CONFIG_CMD_KGDB) 169#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 170#else 171#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 172#endif 173#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 174#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 175#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 176 177#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x10000) 178 179#define CONFIG_SYS_MBAR 0xFC000000 180 181/* 182 * Low Level Configuration Settings 183 * (address mappings, register initial values, etc.) 184 * You should know what you are doing if you make changes here. 185 */ 186 187/* 188 * Definitions for initial stack pointer and data area (in DPRAM) 189 */ 190#define CONFIG_SYS_INIT_RAM_ADDR 0x80000000 191#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* Size of used area in internal SRAM */ 192#define CONFIG_SYS_INIT_RAM_CTRL 0x221 193#define CONFIG_SYS_GBL_DATA_OFFSET ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 32) 194#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32) 195#define CONFIG_SYS_SBFHDR_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - 32) 196 197/* 198 * Start addresses for the final memory configuration 199 * (Set up by the startup code) 200 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 201 */ 202#define CONFIG_SYS_SDRAM_BASE 0x40000000 203#define CONFIG_SYS_SDRAM_SIZE 64 /* SDRAM size in MB */ 204#define CONFIG_SYS_SDRAM_CFG1 0x43711630 205#define CONFIG_SYS_SDRAM_CFG2 0x56670000 206#define CONFIG_SYS_SDRAM_CTRL 0xE1092000 207#define CONFIG_SYS_SDRAM_EMOD 0x81810000 208#define CONFIG_SYS_SDRAM_MODE 0x00CD0000 209#define CONFIG_SYS_SDRAM_DRV_STRENGTH 0x00 210 211#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE + 0x400 212#define CONFIG_SYS_MEMTEST_END ((CONFIG_SYS_SDRAM_SIZE - 3) << 20) 213 214#ifdef CONFIG_CF_SBF 215# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_TEXT_BASE + 0x400) 216#else 217# define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400) 218#endif 219#define CONFIG_SYS_BOOTPARAMS_LEN 64*1024 220#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 221#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 222 223/* Initial Memory map for Linux */ 224#define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) 225#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) 226 227/* 228 * Configuration for environment 229 * Environment is not embedded in u-boot. First time runing may have env 230 * crc error warning if there is no correct environment on the flash. 231 */ 232#ifdef CONFIG_CF_SBF 233# define CONFIG_ENV_IS_IN_SPI_FLASH 234# define CONFIG_ENV_SPI_CS 2 235#else 236# define CONFIG_ENV_IS_IN_FLASH 1 237#endif 238#define CONFIG_ENV_OVERWRITE 1 239 240/*----------------------------------------------------------------------- 241 * FLASH organization 242 */ 243#ifdef CONFIG_SYS_STMICRO_BOOT 244# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 245# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 246# define CONFIG_ENV_OFFSET 0x30000 247# define CONFIG_ENV_SIZE 0x1000 248# define CONFIG_ENV_SECT_SIZE 0x10000 249#endif 250#ifdef CONFIG_SYS_SPANSION_BOOT 251# define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE 252# define CONFIG_SYS_FLASH0_BASE CONFIG_SYS_CS0_BASE 253# define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000) 254# define CONFIG_ENV_SIZE 0x1000 255# define CONFIG_ENV_SECT_SIZE 0x8000 256#endif 257 258#define CONFIG_SYS_FLASH_CFI 259#ifdef CONFIG_SYS_FLASH_CFI 260# define CONFIG_FLASH_CFI_DRIVER 1 261# define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 262# define CONFIG_FLASH_SPANSION_S29WS_N 1 263# define CONFIG_SYS_FLASH_SIZE 0x1000000 /* Max size that the board might have */ 264# define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT 265# define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 266# define CONFIG_SYS_MAX_FLASH_SECT 137 /* max number of sectors on one chip */ 267# define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ 268# define CONFIG_SYS_FLASH_CHECKSUM 269# define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_CS0_BASE } 270#endif 271 272/* 273 * This is setting for JFFS2 support in u-boot. 274 * NOTE: Enable CONFIG_CMD_JFFS2 for JFFS2 support. 275 */ 276#ifdef CONFIG_CMD_JFFS2 277# define CONFIG_JFFS2_DEV "nor0" 278# define CONFIG_JFFS2_PART_SIZE (0x01000000 - 0x40000) 279# define CONFIG_JFFS2_PART_OFFSET (CONFIG_SYS_FLASH0_BASE + 0x40000) 280#endif 281 282/*----------------------------------------------------------------------- 283 * Cache Configuration 284 */ 285#define CONFIG_SYS_CACHELINE_SIZE 16 286 287#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 288 CONFIG_SYS_INIT_RAM_SIZE - 8) 289#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ 290 CONFIG_SYS_INIT_RAM_SIZE - 4) 291#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV | CF_CACR_INVI) 292#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ 293 CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ 294 CF_ACR_EN | CF_ACR_SM_ALL) 295#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_CINV | \ 296 CF_CACR_DISD | CF_CACR_INVI | \ 297 CF_CACR_CEIB | CF_CACR_DCM | \ 298 CF_CACR_EUSP) 299 300/*----------------------------------------------------------------------- 301 * Memory bank definitions 302 */ 303/* 304 * CS0 - NOR Flash 305 * CS1 - Available 306 * CS2 - Available 307 * CS3 - Available 308 * CS4 - Available 309 * CS5 - Available 310 */ 311 312#ifdef CONFIG_CF_SBF 313#define CONFIG_SYS_CS0_BASE 0x04000000 314#define CONFIG_SYS_CS0_MASK 0x00FF0001 315#define CONFIG_SYS_CS0_CTRL 0x00001FA0 316#else 317#define CONFIG_SYS_CS0_BASE 0x00000000 318#define CONFIG_SYS_CS0_MASK 0x00FF0001 319#define CONFIG_SYS_CS0_CTRL 0x00001FA0 320#endif 321 322#endif /* _M52277EVB_H */ 323