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14#ifndef __CONFIG_H
15#define __CONFIG_H
16
17
18
19
20#define CONFIG_E300 1
21#define CONFIG_QE 1
22#define CONFIG_MPC8360 1
23#define CONFIG_MPC8360ERDK 1
24
25#define CONFIG_SYS_TEXT_BASE 0xFF800000
26
27
28
29
30#ifdef CONFIG_CLKIN_33MHZ
31#define CONFIG_83XX_CLKIN 33333333
32#define CONFIG_SYS_CLK_FREQ 33333333
33#define CONFIG_PCI_33M 1
34#define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_10X1
35#else
36#define CONFIG_83XX_CLKIN 66000000
37#define CONFIG_SYS_CLK_FREQ 66000000
38#define CONFIG_PCI_66M 1
39#define HRCWL_CSB_TO_CLKIN_MPC8360ERDK HRCWL_CSB_TO_CLKIN_5X1
40#endif
41
42
43
44
45#define CONFIG_SYS_HRCW_LOW (\
46 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
47 HRCWL_DDR_TO_SCB_CLK_1X1 |\
48 HRCWL_CSB_TO_CLKIN_MPC8360ERDK |\
49 HRCWL_CORE_TO_CSB_2X1 |\
50 HRCWL_CE_TO_PLL_1X15)
51
52#define CONFIG_SYS_HRCW_HIGH (\
53 HRCWH_PCI_HOST |\
54 HRCWH_PCI1_ARBITER_ENABLE |\
55 HRCWH_PCICKDRV_ENABLE |\
56 HRCWH_CORE_ENABLE |\
57 HRCWH_FROM_0X00000100 |\
58 HRCWH_BOOTSEQ_DISABLE |\
59 HRCWH_SW_WATCHDOG_DISABLE |\
60 HRCWH_ROM_LOC_LOCAL_16BIT |\
61 HRCWH_SECONDARY_DDR_DISABLE |\
62 HRCWH_BIG_ENDIAN |\
63 HRCWH_LALE_EARLY)
64
65
66
67
68#define CONFIG_SYS_SICRH 0x00000000
69#define CONFIG_SYS_SICRL 0x40000000
70
71#define CONFIG_BOARD_EARLY_INIT_R
72
73
74
75
76#define CONFIG_SYS_IMMR 0xE0000000
77
78
79
80
81#define CONFIG_SYS_DDR_BASE 0x00000000
82#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
83#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
84#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL (DDR_SDRAM_CLK_CNTL_SS_EN \
85 | DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
86
87#define CONFIG_SYS_83XX_DDR_USES_CS0
88
89#define CONFIG_DDR_ECC
90#define CONFIG_DDR_ECC_CMD
91
92
93
94
95#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \
96 | DDRCDR_ODT \
97 | DDRCDR_Q_DRN)
98
99
100#undef CONFIG_SPD_EEPROM
101
102
103
104
105#define CONFIG_DDR_II
106#define CONFIG_SYS_DDR_SIZE 256
107#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
108#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \
109 | CSCONFIG_ROW_BIT_13 \
110 | CSCONFIG_COL_BIT_10 \
111 | CSCONFIG_ODT_WR_ONLY_CURRENT)
112#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 \
113 | SDRAM_CFG_ECC_EN)
114#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000
115#define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
116#define CONFIG_SYS_DDR_INTERVAL ((256 << SDRAM_INTERVAL_BSTOPRE_SHIFT) \
117 | (1115 << SDRAM_INTERVAL_REFINT_SHIFT))
118#define CONFIG_SYS_DDR_MODE 0x47800432
119#define CONFIG_SYS_DDR_MODE2 0x8000c000
120
121#define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
122 (9 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
123 (3 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
124 (3 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
125 (0 << TIMING_CFG0_WWT_SHIFT) | \
126 (0 << TIMING_CFG0_RRT_SHIFT) | \
127 (0 << TIMING_CFG0_WRT_SHIFT) | \
128 (0 << TIMING_CFG0_RWT_SHIFT))
129
130#define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_30) | \
131 (2 << TIMING_CFG1_WRTORD_SHIFT) | \
132 (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
133 (3 << TIMING_CFG1_WRREC_SHIFT) | \
134 (10 << TIMING_CFG1_REFREC_SHIFT) | \
135 (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
136 (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
137 (3 << TIMING_CFG1_PRETOACT_SHIFT))
138
139#define CONFIG_SYS_DDR_TIMING_2 ((9 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
140 (4 << TIMING_CFG2_CKE_PLS_SHIFT) | \
141 (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
142 (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
143 (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
144 (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
145 (0 << TIMING_CFG2_CPO_SHIFT))
146
147#define CONFIG_SYS_DDR_TIMING_3 0x00000000
148
149
150
151
152#undef CONFIG_SYS_DRAM_TEST
153#define CONFIG_SYS_MEMTEST_START 0x00000000
154#define CONFIG_SYS_MEMTEST_END 0x00100000
155
156
157
158
159#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
160#define CONFIG_SYS_FLASH_BASE 0xFF800000
161
162#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
163#define CONFIG_SYS_RAMBOOT
164#else
165#undef CONFIG_SYS_RAMBOOT
166#endif
167
168#define CONFIG_SYS_MONITOR_LEN (384 * 1024)
169#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
170
171
172
173
174#define CONFIG_SYS_INIT_RAM_LOCK 1
175#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000
176#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
177#define CONFIG_SYS_GBL_DATA_OFFSET \
178 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
179
180
181
182
183#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
184#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4
185#define CONFIG_SYS_LBC_LBCR 0x00000000
186
187
188
189
190#define CONFIG_SYS_FLASH_CFI
191#define CONFIG_FLASH_CFI_DRIVER
192#define CONFIG_SYS_FLASH_SIZE 8
193#define CONFIG_SYS_FLASH_PROTECTION 1
194
195
196#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE
197#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB)
198
199#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \
200 | BR_PS_16 \
201 | BR_MS_GPCM \
202 | BR_V)
203#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \
204 | OR_UPM_XAM \
205 | OR_GPCM_CSNT \
206 | OR_GPCM_ACS_DIV2 \
207 | OR_GPCM_XACS \
208 | OR_GPCM_SCY_15 \
209 | OR_GPCM_TRLX_SET \
210 | OR_GPCM_EHTR_SET \
211 | OR_GPCM_EAD)
212
213#define CONFIG_SYS_MAX_FLASH_BANKS 1
214#define CONFIG_SYS_MAX_FLASH_SECT 256
215
216#undef CONFIG_SYS_FLASH_CHECKSUM
217
218
219
220
221#define CONFIG_SYS_NAND_BASE 0x60000000
222#define CONFIG_CMD_NAND 1
223#define CONFIG_NAND_FSL_UPM 1
224#define CONFIG_SYS_MAX_NAND_DEVICE 1
225#define CONFIG_MTD_NAND_VERIFY_WRITE
226
227#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
228
229
230
231
232#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256MB)
233
234
235#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \
236 | BR_PS_8 \
237 | BR_MS_UPMA \
238 | BR_V)
239
240#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | OR_UPM_EAD)
241
242
243
244
245
246#define CONFIG_SYS_VIDEO_BASE 0x70000000
247
248#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VIDEO_BASE
249#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB)
250
251
252#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VIDEO_BASE \
253 | BR_PS_32 \
254 | BR_MS_UPMB \
255 | BR_V)
256
257#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB | OR_UPM_EAD)
258
259
260
261
262
263#define CONFIG_CONS_INDEX 1
264#define CONFIG_SYS_NS16550
265#define CONFIG_SYS_NS16550_SERIAL
266#define CONFIG_SYS_NS16550_REG_SIZE 1
267#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
268
269#define CONFIG_SYS_BAUDRATE_TABLE \
270 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
271
272#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
273#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
274
275#define CONFIG_CMDLINE_EDITING 1
276#define CONFIG_AUTO_COMPLETE
277
278#define CONFIG_SYS_HUSH_PARSER
279
280
281#define CONFIG_OF_LIBFDT 1
282#define CONFIG_OF_BOARD_SETUP 1
283#define CONFIG_OF_STDOUT_VIA_ALIAS
284
285
286#define CONFIG_SYS_I2C
287#define CONFIG_SYS_I2C_FSL
288#define CONFIG_SYS_FSL_I2C_SPEED 400000
289#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
290#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
291#define CONFIG_SYS_FSL_I2C2_SPEED 400000
292#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
293#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
294#define CONFIG_SYS_I2C_NOPROBES { {0, 0x52} }
295
296
297
298
299
300#define CONFIG_PCI
301
302#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
303#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
304#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
305#define CONFIG_SYS_PCI1_MMIO_BASE 0x90000000
306#define CONFIG_SYS_PCI1_MMIO_PHYS CONFIG_SYS_PCI1_MMIO_BASE
307#define CONFIG_SYS_PCI1_MMIO_SIZE 0x10000000
308#define CONFIG_SYS_PCI1_IO_BASE 0xE0300000
309#define CONFIG_SYS_PCI1_IO_PHYS 0xE0300000
310#define CONFIG_SYS_PCI1_IO_SIZE 0x100000
311
312#ifdef CONFIG_PCI
313#define CONFIG_PCI_INDIRECT_BRIDGE
314
315#define CONFIG_PCI_PNP
316
317#undef CONFIG_EEPRO100
318#undef CONFIG_PCI_SCAN_SHOW
319#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957
320
321#endif
322
323
324
325
326#define CONFIG_UEC_ETH
327#define CONFIG_ETHPRIME "UEC0"
328
329#define CONFIG_UEC_ETH1
330
331#ifdef CONFIG_UEC_ETH1
332#define CONFIG_SYS_UEC1_UCC_NUM 0
333#define CONFIG_SYS_UEC1_RX_CLK QE_CLK_NONE
334#define CONFIG_SYS_UEC1_TX_CLK QE_CLK9
335#define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH
336#define CONFIG_SYS_UEC1_PHY_ADDR 2
337#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID
338#define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000
339#endif
340
341#define CONFIG_UEC_ETH2
342
343#ifdef CONFIG_UEC_ETH2
344#define CONFIG_SYS_UEC2_UCC_NUM 1
345#define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE
346#define CONFIG_SYS_UEC2_TX_CLK QE_CLK4
347#define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH
348#define CONFIG_SYS_UEC2_PHY_ADDR 4
349#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_RXID
350#define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000
351#endif
352
353
354
355
356
357#ifndef CONFIG_SYS_RAMBOOT
358#define CONFIG_ENV_IS_IN_FLASH 1
359#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
360#define CONFIG_ENV_SECT_SIZE 0x20000
361#define CONFIG_ENV_SIZE 0x20000
362#else
363#define CONFIG_SYS_NO_FLASH 1
364#define CONFIG_ENV_IS_NOWHERE 1
365#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
366#define CONFIG_ENV_SIZE 0x2000
367#endif
368
369#define CONFIG_LOADS_ECHO 1
370#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
371
372
373
374
375#define CONFIG_BOOTP_BOOTFILESIZE
376#define CONFIG_BOOTP_BOOTPATH
377#define CONFIG_BOOTP_GATEWAY
378#define CONFIG_BOOTP_HOSTNAME
379
380
381
382
383
384#include <config_cmd_default.h>
385
386#define CONFIG_CMD_PING
387#define CONFIG_CMD_I2C
388#define CONFIG_CMD_ASKENV
389#define CONFIG_CMD_DHCP
390
391#if defined(CONFIG_PCI)
392#define CONFIG_CMD_PCI
393#endif
394
395#if defined(CONFIG_SYS_RAMBOOT)
396#undef CONFIG_CMD_SAVEENV
397#undef CONFIG_CMD_LOADS
398#endif
399
400#undef CONFIG_WATCHDOG
401
402
403
404
405#define CONFIG_SYS_LONGHELP
406#define CONFIG_SYS_LOAD_ADDR 0x2000000
407
408#if defined(CONFIG_CMD_KGDB)
409 #define CONFIG_SYS_CBSIZE 1024
410#else
411 #define CONFIG_SYS_CBSIZE 256
412#endif
413
414
415#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
416#define CONFIG_SYS_MAXARGS 16
417
418#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
419
420
421
422
423
424
425#define CONFIG_SYS_BOOTMAPSZ (256 << 20)
426
427
428
429
430#define CONFIG_SYS_HID0_INIT 0x000000000
431#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
432 HID0_ENABLE_INSTRUCTION_CACHE)
433#define CONFIG_SYS_HID2 HID2_HBE
434
435
436
437
438
439#define CONFIG_HIGH_BATS 1
440
441
442#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \
443 | BATL_PP_RW \
444 | BATL_MEMCOHERENCE)
445#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \
446 | BATU_BL_256M \
447 | BATU_VS \
448 | BATU_VP)
449#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
450#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
451
452
453#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \
454 | BATL_PP_RW \
455 | BATL_CACHEINHIBIT \
456 | BATL_GUARDEDSTORAGE)
457#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \
458 | BATU_BL_4M \
459 | BATU_VS \
460 | BATU_VP)
461#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
462#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
463
464
465#define CONFIG_SYS_IBAT2L (CONFIG_SYS_NAND_BASE \
466 | BATL_PP_RW \
467 | BATL_CACHEINHIBIT \
468 | BATL_GUARDEDSTORAGE)
469#define CONFIG_SYS_IBAT2U (CONFIG_SYS_NAND_BASE \
470 | BATU_BL_64M \
471 | BATU_VS \
472 | BATU_VP)
473#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
474#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
475
476
477#define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \
478 | BATL_PP_RW \
479 | BATL_MEMCOHERENCE)
480#define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \
481 | BATU_BL_32M \
482 | BATU_VS \
483 | BATU_VP)
484#define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \
485 | BATL_PP_RW \
486 | BATL_CACHEINHIBIT \
487 | BATL_GUARDEDSTORAGE)
488#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
489
490
491#define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR \
492 | BATL_PP_RW)
493#define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \
494 | BATU_BL_128K \
495 | BATU_VS \
496 | BATU_VP)
497#define CONFIG_SYS_DBAT4L CONFIG_SYS_IBAT4L
498#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
499
500#define CONFIG_SYS_IBAT5L (CONFIG_SYS_VIDEO_BASE \
501 | BATL_PP_RW \
502 | BATL_CACHEINHIBIT \
503 | BATL_GUARDEDSTORAGE)
504#define CONFIG_SYS_IBAT5U (CONFIG_SYS_VIDEO_BASE \
505 | BATU_BL_64M \
506 | BATU_VS \
507 | BATU_VP)
508#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
509#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
510
511#ifdef CONFIG_PCI
512
513#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \
514 | BATL_PP_RW \
515 | BATL_MEMCOHERENCE)
516#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \
517 | BATU_BL_256M \
518 | BATU_VS \
519 | BATU_VP)
520#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
521#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
522
523#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \
524 | BATL_PP_RW \
525 | BATL_CACHEINHIBIT \
526 | BATL_GUARDEDSTORAGE)
527#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \
528 | BATU_BL_256M \
529 | BATU_VS \
530 | BATU_VP)
531#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
532#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
533#else
534#define CONFIG_SYS_IBAT6L (0)
535#define CONFIG_SYS_IBAT6U (0)
536#define CONFIG_SYS_IBAT7L (0)
537#define CONFIG_SYS_IBAT7U (0)
538#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
539#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
540#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
541#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
542#endif
543
544#if defined(CONFIG_CMD_KGDB)
545#define CONFIG_KGDB_BAUDRATE 230400
546#endif
547
548
549
550
551#define CONFIG_ENV_OVERWRITE
552
553#if defined(CONFIG_UEC_ETH)
554#define CONFIG_HAS_ETH0
555#define CONFIG_HAS_ETH1
556#define CONFIG_HAS_ETH2
557#define CONFIG_HAS_ETH3
558#endif
559
560#define CONFIG_BAUDRATE 115200
561
562#define CONFIG_LOADADDR a00000
563#define CONFIG_HOSTNAME mpc8360erdk
564#define CONFIG_BOOTFILE "uImage"
565
566#define CONFIG_ROOTPATH "/nfsroot/"
567
568#define CONFIG_BOOTDELAY 2
569#undef CONFIG_BOOTARGS
570
571#define CONFIG_EXTRA_ENV_SETTINGS \
572 "netdev=eth0\0" \
573 "consoledev=ttyS0\0" \
574 "loadaddr=a00000\0" \
575 "fdtaddr=900000\0" \
576 "fdtfile=mpc836x_rdk.dtb\0" \
577 "fsfile=fs\0" \
578 "ubootfile=u-boot.bin\0" \
579 "mtdparts=mtdparts=60000000.nand-flash:4096k(kernel),128k(dtb),"\
580 "-(rootfs)\0" \
581 "setbootargs=setenv bootargs console=$consoledev,$baudrate " \
582 "$mtdparts panic=1\0" \
583 "adddhcpargs=setenv bootargs $bootargs ip=on\0" \
584 "addnfsargs=setenv bootargs $bootargs ip=$ipaddr:$serverip:" \
585 "$gatewayip:$netmask:$hostname:$netdev:off " \
586 "root=/dev/nfs rw nfsroot=$serverip:$rootpath\0" \
587 "addnandargs=setenv bootargs $bootargs root=/dev/mtdblock3 " \
588 "rootfstype=jffs2 rw\0" \
589 "tftp_get_uboot=tftp 100000 $ubootfile\0" \
590 "tftp_get_kernel=tftp $loadaddr $bootfile\0" \
591 "tftp_get_dtb=tftp $fdtaddr $fdtfile\0" \
592 "tftp_get_fs=tftp c00000 $fsfile\0" \
593 "nand_erase_kernel=nand erase 0 400000\0" \
594 "nand_erase_dtb=nand erase 400000 20000\0" \
595 "nand_erase_fs=nand erase 420000 3be0000\0" \
596 "nand_write_kernel=nand write.jffs2 $loadaddr 0 400000\0" \
597 "nand_write_dtb=nand write.jffs2 $fdtaddr 400000 20000\0" \
598 "nand_write_fs=nand write.jffs2 c00000 420000 $filesize\0" \
599 "nand_read_kernel=nand read.jffs2 $loadaddr 0 400000\0" \
600 "nand_read_dtb=nand read.jffs2 $fdtaddr 400000 20000\0" \
601 "nor_reflash=protect off ff800000 ff87ffff ; " \
602 "erase ff800000 ff87ffff ; " \
603 "cp.b 100000 ff800000 $filesize\0" \
604 "nand_reflash_kernel=run tftp_get_kernel nand_erase_kernel " \
605 "nand_write_kernel\0" \
606 "nand_reflash_dtb=run tftp_get_dtb nand_erase_dtb nand_write_dtb\0"\
607 "nand_reflash_fs=run tftp_get_fs nand_erase_fs nand_write_fs\0" \
608 "nand_reflash=run nand_reflash_kernel nand_reflash_dtb " \
609 "nand_reflash_fs\0" \
610 "boot_m=bootm $loadaddr - $fdtaddr\0" \
611 "dhcpboot=dhcp ; run setbootargs adddhcpargs tftp_get_dtb boot_m\0"\
612 "nfsboot=run setbootargs addnfsargs tftp_get_kernel tftp_get_dtb "\
613 "boot_m\0" \
614 "nandboot=run setbootargs addnandargs nand_read_kernel nand_read_dtb "\
615 "boot_m\0" \
616 ""
617
618#define CONFIG_BOOTCOMMAND "run dhcpboot"
619
620#endif
621