1
2
3
4
5
6
7
8
9
10
11
12
13#ifndef __CONFIG_H
14#define __CONFIG_H
15
16
17#define CONFIG_MPC8610 1
18#define CONFIG_MPC8610HPCD 1
19#define CONFIG_LINUX_RESET_VEC 0x100
20
21#define CONFIG_SYS_TEXT_BASE 0xfff00000
22
23
24
25#define CONFIG_FSL_DIU_FB
26
27#ifdef CONFIG_FSL_DIU_FB
28#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x2c000)
29#define CONFIG_VIDEO
30#define CONFIG_CMD_BMP
31#define CONFIG_CFB_CONSOLE
32#define CONFIG_VIDEO_SW_CURSOR
33#define CONFIG_VGA_AS_SINGLE_DEVICE
34#define CONFIG_VIDEO_LOGO
35#define CONFIG_VIDEO_BMP_LOGO
36#endif
37
38#ifdef RUN_DIAG
39#define CONFIG_SYS_DIAG_ADDR 0xff800000
40#endif
41
42
43
44
45
46#define CONFIG_SYS_SCRATCH_VA 0xc0000000
47
48#define CONFIG_PCI 1
49#define CONFIG_PCI1 1
50#define CONFIG_PCIE1 1
51#define CONFIG_PCIE2 1
52#define CONFIG_FSL_PCI_INIT 1
53#define CONFIG_PCI_INDIRECT_BRIDGE 1
54#define CONFIG_SYS_PCI_64BIT 1
55#define CONFIG_FSL_LAW 1
56
57#define CONFIG_ENV_OVERWRITE
58#define CONFIG_INTERRUPTS
59
60#define CONFIG_BAT_RW 1
61#define CONFIG_HIGH_BATS 1
62#define CONFIG_ALTIVEC 1
63
64
65
66
67#define CONFIG_SYS_L2
68#define L2_INIT 0
69#define L2_ENABLE (L2CR_L2E |0x00100000 )
70
71#ifndef CONFIG_SYS_CLK_FREQ
72#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
73#endif
74
75#define CONFIG_BOARD_EARLY_INIT_F 1
76#define CONFIG_MISC_INIT_R 1
77
78#define CONFIG_SYS_MEMTEST_START 0x00200000
79#define CONFIG_SYS_MEMTEST_END 0x00400000
80
81
82
83
84
85#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000
86#define CONFIG_SYS_CCSRBAR 0xe0000000
87#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR
88
89#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
90#define CONFIG_SYS_CCSRBAR_PHYS_HIGH 0x0
91#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW
92
93
94#define CONFIG_SYS_FSL_DDR2
95#undef CONFIG_FSL_DDR_INTERACTIVE
96#define CONFIG_SPD_EEPROM
97#define CONFIG_DDR_SPD
98
99#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
100#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
101
102#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
103#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
104#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000
105#define CONFIG_VERY_BIG_RAM
106
107#define CONFIG_NUM_DDR_CONTROLLERS 1
108#define CONFIG_DIMM_SLOTS_PER_CTLR 1
109#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
110
111#define SPD_EEPROM_ADDRESS 0x51
112
113
114#define CONFIG_SYS_SDRAM_SIZE 256
115
116#if 0
117#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000F
118#define CONFIG_SYS_DDR_CS0_CONFIG 0x80010202
119#define CONFIG_SYS_DDR_TIMING_3 0x00000000
120#define CONFIG_SYS_DDR_TIMING_0 0x00260802
121#define CONFIG_SYS_DDR_TIMING_1 0x3935d322
122#define CONFIG_SYS_DDR_TIMING_2 0x14904cc8
123#define CONFIG_SYS_DDR_MODE_1 0x00480432
124#define CONFIG_SYS_DDR_MODE_2 0x00000000
125#define CONFIG_SYS_DDR_INTERVAL 0x06180100
126#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
127#define CONFIG_SYS_DDR_CLK_CTRL 0x03800000
128#define CONFIG_SYS_DDR_OCD_CTRL 0x00000000
129#define CONFIG_SYS_DDR_OCD_STATUS 0x00000000
130#define CONFIG_SYS_DDR_CONTROL 0xe3008000
131#define CONFIG_SYS_DDR_CONTROL2 0x04400010
132
133#define CONFIG_SYS_DDR_ERR_INT_EN 0x00000000
134#define CONFIG_SYS_DDR_ERR_DIS 0x00000000
135#define CONFIG_SYS_DDR_SBE 0x000f0000
136
137#endif
138
139
140#define CONFIG_ID_EEPROM
141#define CONFIG_SYS_I2C_EEPROM_NXID
142#define CONFIG_ID_EEPROM
143#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
144#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
145
146
147#define CONFIG_SYS_FLASH_BASE 0xf0000000
148#define CONFIG_SYS_FLASH_BASE2 0xf8000000
149
150#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE2}
151
152#define CONFIG_SYS_BR0_PRELIM 0xf8001001
153#define CONFIG_SYS_OR0_PRELIM 0xf8006e65
154
155#define CONFIG_SYS_BR1_PRELIM 0xf0001001
156#define CONFIG_SYS_OR1_PRELIM 0xf8006e65
157#if 0
158#define CONFIG_SYS_BR2_PRELIM 0xf0000000
159#define CONFIG_SYS_OR2_PRELIM 0xf0000000
160#endif
161#define CONFIG_SYS_BR3_PRELIM 0xe8000801
162#define CONFIG_SYS_OR3_PRELIM 0xfff06ff7
163
164
165#define CONFIG_FSL_PIXIS 1
166#define PIXIS_BASE 0xe8000000
167#define PIXIS_ID 0x0
168#define PIXIS_VER 0x1
169#define PIXIS_PVER 0x2
170#define PIXIS_RST 0x4
171#define PIXIS_AUX 0x6
172#define PIXIS_SPD 0x7
173#define PIXIS_BRDCFG0 0x8
174#define PIXIS_VCTL 0x10
175#define PIXIS_VCFGEN0 0x12
176#define PIXIS_VCFGEN1 0x13
177#define PIXIS_VBOOT 0x16
178#define PIXIS_VSPEED0 0x17
179#define PIXIS_VSPEED1 0x18
180#define PIXIS_VCLKH 0x19
181#define PIXIS_VCLKL 0x1A
182#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xC0
183
184#define CONFIG_SYS_MAX_FLASH_BANKS 2
185#define CONFIG_SYS_MAX_FLASH_SECT 1024
186
187#undef CONFIG_SYS_FLASH_CHECKSUM
188#define CONFIG_SYS_FLASH_ERASE_TOUT 60000
189#define CONFIG_SYS_FLASH_WRITE_TOUT 500
190#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
191#define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000
192
193#define CONFIG_FLASH_CFI_DRIVER
194#define CONFIG_SYS_FLASH_CFI
195#define CONFIG_SYS_FLASH_EMPTY_INFO
196
197#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
198#define CONFIG_SYS_RAMBOOT
199#else
200#undef CONFIG_SYS_RAMBOOT
201#endif
202
203#if defined(CONFIG_SYS_RAMBOOT)
204#undef CONFIG_SPD_EEPROM
205#define CONFIG_SYS_SDRAM_SIZE 256
206#endif
207
208#undef CONFIG_CLOCKS_IN_MHZ
209
210#define CONFIG_SYS_INIT_RAM_LOCK 1
211#ifndef CONFIG_SYS_INIT_RAM_LOCK
212#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000
213#else
214#define CONFIG_SYS_INIT_RAM_ADDR 0xe4000000
215#endif
216#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
217
218#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
219#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
220
221#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
222#define CONFIG_SYS_MALLOC_LEN (6 * 1024 * 1024)
223
224
225#define CONFIG_CONS_INDEX 1
226#define CONFIG_SYS_NS16550
227#define CONFIG_SYS_NS16550_SERIAL
228#define CONFIG_SYS_NS16550_REG_SIZE 1
229#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
230
231#define CONFIG_SYS_BAUDRATE_TABLE \
232 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
233
234#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
235#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
236
237
238#define CONFIG_SYS_HUSH_PARSER
239
240
241
242
243#define CONFIG_OF_LIBFDT 1
244#define CONFIG_OF_BOARD_SETUP 1
245#define CONFIG_OF_STDOUT_VIA_ALIAS 1
246
247
248
249#define OF_FLAT_TREE_MAX_SIZE 8192
250
251
252
253
254#define CONFIG_SYS_I2C
255#define CONFIG_SYS_I2C_FSL
256#define CONFIG_SYS_FSL_I2C_SPEED 400000
257#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
258#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
259#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} }
260
261
262
263
264
265#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
266#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BUS
267#define CONFIG_SYS_PCI1_MEM_VIRT CONFIG_SYS_PCI1_MEM_BUS
268#define CONFIG_SYS_PCI1_MEM_SIZE 0x10000000
269#define CONFIG_SYS_PCI1_IO_BUS 0x0000000
270#define CONFIG_SYS_PCI1_IO_PHYS 0xe1000000
271#define CONFIG_SYS_PCI1_IO_VIRT 0xe1000000
272#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000
273
274
275#define CONFIG_SYS_PCIE1_NAME "ULI"
276#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
277#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BUS
278#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
279#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
280#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
281#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000
282
283
284#define CONFIG_SYS_PCIE2_NAME "Slot 1"
285#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000
286#define CONFIG_SYS_PCIE2_MEM_PHYS CONFIG_SYS_PCIE2_MEM_BUS
287#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
288#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
289#define CONFIG_SYS_PCIE2_IO_PHYS 0xe2000000
290#define CONFIG_SYS_PCIE2_IO_SIZE 0x00100000
291
292
293#if defined(CONFIG_PCI)
294
295#define CONFIG_PCI_SCAN_SHOW
296
297#define CONFIG_CMD_NET
298#define CONFIG_PCI_PNP
299#define CONFIG_CMD_REGINFO
300
301#define CONFIG_ULI526X
302#ifdef CONFIG_ULI526X
303#define CONFIG_ETHADDR 00:E0:0C:00:00:01
304#endif
305
306
307
308
309#define CONFIG_PCI_OHCI 1
310#define CONFIG_USB_OHCI_NEW 1
311#define CONFIG_USB_KEYBOARD 1
312#define CONFIG_SYS_STDIO_DEREGISTER
313#define CONFIG_SYS_USB_EVENT_POLL 1
314#define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci"
315#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
316#define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
317
318#if !defined(CONFIG_PCI_PNP)
319#define PCI_ENET0_IOADDR 0xe0000000
320#define PCI_ENET0_MEMADDR 0xe0000000
321#define PCI_IDSEL_NUMBER 0x0c
322#endif
323
324#define CONFIG_DOS_PARTITION
325#define CONFIG_SCSI_AHCI
326
327#ifdef CONFIG_SCSI_AHCI
328#define CONFIG_LIBATA
329#define CONFIG_SATA_ULI5288
330#define CONFIG_SYS_SCSI_MAX_SCSI_ID 4
331#define CONFIG_SYS_SCSI_MAX_LUN 1
332#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN)
333#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE
334#endif
335
336#endif
337
338
339
340
341
342#define CONFIG_SYS_DBAT0L (BATL_PP_RW)
343#define CONFIG_SYS_IBAT0L (BATL_PP_RW)
344
345
346
347
348
349
350
351
352#define CONFIG_SYS_DBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
353 | BATL_GUARDEDSTORAGE)
354#define CONFIG_SYS_DBAT1U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G | BATU_VS | BATU_VP)
355#define CONFIG_SYS_IBAT1L (CONFIG_SYS_PCI1_MEM_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
356#define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U
357
358
359
360
361
362
363#define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
364 | BATL_GUARDEDSTORAGE)
365#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_16M | BATU_VS | BATU_VP)
366#define CONFIG_SYS_IBAT2L (CONFIG_SYS_PCI1_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
367#define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
368
369
370
371
372
373
374#define CONFIG_SYS_DBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT \
375 | BATL_GUARDEDSTORAGE)
376#define CONFIG_SYS_DBAT3U (CONFIG_SYS_CCSRBAR | BATU_BL_1M | BATU_VS | BATU_VP)
377#define CONFIG_SYS_IBAT3L (CONFIG_SYS_CCSRBAR | BATL_PP_RW | BATL_CACHEINHIBIT)
378#define CONFIG_SYS_IBAT3U CONFIG_SYS_DBAT3U
379
380#if (CONFIG_SYS_CCSRBAR_DEFAULT != CONFIG_SYS_CCSRBAR)
381#define CONFIG_SYS_CCSR_DEFAULT_DBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
382 | BATL_PP_RW | BATL_CACHEINHIBIT \
383 | BATL_GUARDEDSTORAGE)
384#define CONFIG_SYS_CCSR_DEFAULT_DBATU (CONFIG_SYS_CCSRBAR_DEFAULT \
385 | BATU_BL_1M | BATU_VS | BATU_VP)
386#define CONFIG_SYS_CCSR_DEFAULT_IBATL (CONFIG_SYS_CCSRBAR_DEFAULT \
387 | BATL_PP_RW | BATL_CACHEINHIBIT)
388#define CONFIG_SYS_CCSR_DEFAULT_IBATU CONFIG_SYS_CCSR_DEFAULT_DBATU
389#endif
390
391
392
393
394
395
396
397#define CONFIG_SYS_DBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT \
398 | BATL_GUARDEDSTORAGE)
399#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE2_IO_PHYS | BATU_BL_32M | BATU_VS | BATU_VP)
400#define CONFIG_SYS_IBAT4L (CONFIG_SYS_PCIE2_IO_PHYS | BATL_PP_RW | BATL_CACHEINHIBIT)
401#define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U
402
403
404
405
406
407
408#define CONFIG_SYS_DBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
409#define CONFIG_SYS_DBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
410#define CONFIG_SYS_IBAT5L CONFIG_SYS_DBAT5L
411#define CONFIG_SYS_IBAT5U CONFIG_SYS_DBAT5U
412
413
414
415
416
417#define CONFIG_SYS_DBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
418 | BATL_GUARDEDSTORAGE)
419#define CONFIG_SYS_DBAT6U (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
420#define CONFIG_SYS_IBAT6L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | BATL_MEMCOHERENCE)
421#define CONFIG_SYS_IBAT6U CONFIG_SYS_DBAT6U
422
423
424#define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
425 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
426#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
427#define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \
428 | BATL_MEMCOHERENCE)
429#define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY
430
431
432
433
434
435#define CONFIG_SYS_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \
436 | BATL_GUARDEDSTORAGE)
437#define CONFIG_SYS_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP)
438#define CONFIG_SYS_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
439#define CONFIG_SYS_IBAT7U CONFIG_SYS_DBAT7U
440
441
442
443
444
445#ifndef CONFIG_SYS_RAMBOOT
446#define CONFIG_ENV_IS_IN_FLASH 1
447#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
448#define CONFIG_ENV_SECT_SIZE 0x20000
449#define CONFIG_ENV_SIZE 0x2000
450#else
451#define CONFIG_ENV_IS_NOWHERE 1
452#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
453#define CONFIG_ENV_SIZE 0x2000
454#endif
455
456#define CONFIG_LOADS_ECHO 1
457#define CONFIG_SYS_LOADS_BAUD_CHANGE 1
458
459
460
461
462
463#define CONFIG_BOOTP_BOOTFILESIZE
464#define CONFIG_BOOTP_BOOTPATH
465#define CONFIG_BOOTP_GATEWAY
466#define CONFIG_BOOTP_HOSTNAME
467
468
469
470
471
472#include <config_cmd_default.h>
473
474#define CONFIG_CMD_PING
475#define CONFIG_CMD_I2C
476#define CONFIG_CMD_MII
477
478#if defined(CONFIG_SYS_RAMBOOT)
479#undef CONFIG_CMD_SAVEENV
480#endif
481
482#if defined(CONFIG_PCI)
483#define CONFIG_CMD_PCI
484#define CONFIG_CMD_SCSI
485#define CONFIG_CMD_EXT2
486#define CONFIG_CMD_USB
487#endif
488
489
490#define CONFIG_WATCHDOG
491#define CONFIG_SYS_WATCHDOG_FREQ 5000
492
493
494
495
496#define CONFIG_SYS_LONGHELP
497#define CONFIG_CMDLINE_EDITING
498#define CONFIG_SYS_LOAD_ADDR 0x2000000
499
500#if defined(CONFIG_CMD_KGDB)
501#define CONFIG_SYS_CBSIZE 1024
502#else
503#define CONFIG_SYS_CBSIZE 256
504#endif
505
506#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
507#define CONFIG_SYS_MAXARGS 16
508#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
509
510
511
512
513
514
515#define CONFIG_SYS_BOOTMAPSZ (8 << 20)
516
517#if defined(CONFIG_CMD_KGDB)
518#define CONFIG_KGDB_BAUDRATE 230400
519#endif
520
521
522
523
524#define CONFIG_IPADDR 192.168.1.100
525
526#define CONFIG_HOSTNAME unknown
527#define CONFIG_ROOTPATH "/opt/nfsroot"
528#define CONFIG_BOOTFILE "uImage"
529#define CONFIG_UBOOTPATH 8610hpcd/u-boot.bin
530
531#define CONFIG_SERVERIP 192.168.1.1
532#define CONFIG_GATEWAYIP 192.168.1.1
533#define CONFIG_NETMASK 255.255.255.0
534
535
536#define CONFIG_LOADADDR 1000000
537
538#define CONFIG_BOOTDELAY 10
539#undef CONFIG_BOOTARGS
540
541#define CONFIG_BAUDRATE 115200
542
543#if defined(CONFIG_PCI1)
544#define PCI_ENV \
545 "pcireg=md ${a}000 3; echo o;md ${a}c00 25; echo i; md ${a}da0 15;" \
546 "echo e;md ${a}e00 9\0" \
547 "pci1regs=setenv a e0008; run pcireg\0" \
548 "pcierr=md ${a}e00 8; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;" \
549 "pci d.w $b.0 56 1\0" \
550 "pcierrc=mw ${a}e00 ffffffff; pci w.b $b.0 7 ff; pci w.w $b.0 1e ffff;" \
551 "pci w.w $b.0 56 ffff\0" \
552 "pci1err=setenv a e0008; run pcierr\0" \
553 "pci1errc=setenv a e0008; run pcierrc\0"
554#else
555#define PCI_ENV ""
556#endif
557
558#if defined(CONFIG_PCIE1) || defined(CONFIG_PCIE2)
559#define PCIE_ENV \
560 "pciereg=md ${a}000 6; md ${a}020 4; md ${a}bf8 2; echo o;md ${a}c00 25;" \
561 "echo i; md ${a}da0 15; echo e;md ${a}e00 e; echo d; md ${a}f00 c\0" \
562 "pcie1regs=setenv a e000a; run pciereg\0" \
563 "pcie2regs=setenv a e0009; run pciereg\0" \
564 "pcieerr=md ${a}020 1; md ${a}e00; pci d.b $b.0 7 1; pci d.w $b.0 1e 1;"\
565 "pci d.w $b.0 56 1; pci d $b.0 104 1; pci d $b.0 110 1;" \
566 "pci d $b.0 130 1\0" \
567 "pcieerrc=mw ${a}020 ffffffff; mw ${a}e00 ffffffff; pci w.b $b.0 7 ff;"\
568 "pci w.w $b.0 1e ffff; pci w.w $b.0 56 ffff; pci w $b.0 104 ffffffff;" \
569 "pci w $b.0 110 ffffffff; pci w $b.0 130 ffffffff\0" \
570 "pciecfg=pci d $b.0 0 20; pci d $b.0 100 e; pci d $b.0 400 69\0" \
571 "pcie1err=setenv a e000a; run pcieerr\0" \
572 "pcie2err=setenv a e0009; run pcieerr\0" \
573 "pcie1errc=setenv a e000a; run pcieerrc\0" \
574 "pcie2errc=setenv a e0009; run pcieerrc\0"
575#else
576#define PCIE_ENV ""
577#endif
578
579#define DMA_ENV \
580 "dma0=mw ${d}104 ffffffff;mw ${d}110 50000;mw ${d}114 $sad0;mw ${d}118 50000;"\
581 "mw ${d}120 $bc0;mw ${d}100 f03c404; mw ${d}11c $dad0; md ${d}100 9\0" \
582 "dma1=mw ${d}184 ffffffff;mw ${d}190 50000;mw ${d}194 $sad1;mw ${d}198 50000;"\
583 "mw ${d}1a0 $bc1;mw ${d}180 f03c404; mw ${d}19c $dad1; md ${d}180 9\0" \
584 "dma2=mw ${d}204 ffffffff;mw ${d}210 50000;mw ${d}214 $sad2;mw ${d}218 50000;"\
585 "mw ${d}220 $bc2;mw ${d}200 f03c404; mw ${d}21c $dad2; md ${d}200 9\0" \
586 "dma3=mw ${d}284 ffffffff;mw ${d}290 50000;mw ${d}294 $sad3;mw ${d}298 50000;"\
587 "mw ${d}2a0 $bc3;mw ${d}280 f03c404; mw ${d}29c $dad3; md ${d}280 9\0"
588
589#ifdef ENV_DEBUG
590#define CONFIG_EXTRA_ENV_SETTINGS \
591"netdev=eth0\0" \
592"uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
593"tftpflash=tftpboot $loadaddr $uboot; " \
594 "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \
595 " +$filesize; " \
596 "erase " __stringify(CONFIG_SYS_TEXT_BASE) \
597 " +$filesize; " \
598 "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
599 " $filesize; " \
600 "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \
601 " +$filesize; " \
602 "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \
603 " $filesize\0" \
604"consoledev=ttyS0\0" \
605"ramdiskaddr=2000000\0" \
606"ramdiskfile=8610hpcd/ramdisk.uboot\0" \
607"fdtaddr=c00000\0" \
608"fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
609"bdev=sda3\0" \
610"en-wd=mw.b f8100010 0x08; echo -expect:- 08; md.b f8100010 1\0" \
611"dis-wd=mw.b f8100010 0x00; echo -expect:- 00; md.b f8100010 1\0" \
612"maxcpus=1" \
613"eoi=mw e00400b0 0\0" \
614"iack=md e00400a0 1\0" \
615"ddrreg=md ${a}000 8; md ${a}080 8;md ${a}100 d; md ${a}140 4;" \
616 "md ${a}bf0 4; md ${a}e00 3; md ${a}e20 3; md ${a}e40 7;" \
617 "md ${a}f00 5\0" \
618"ddr1regs=setenv a e0002; run ddrreg\0" \
619"gureg=md ${a}000 2c; md ${a}0b0 1; md ${a}0c0 1; md ${a}800 1;" \
620 "md ${a}900 6; md ${a}a00 1; md ${a}b20 3; md ${a}e00 1;" \
621 "md ${a}e60 1; md ${a}ef0 1d\0" \
622"guregs=setenv a e00e0; run gureg\0" \
623"mcmreg=md ${a}000 1b; md ${a}bf8 2; md ${a}e00 5\0" \
624"mcmregs=setenv a e0001; run mcmreg\0" \
625"diuregs=md e002c000 1d\0" \
626"dium=mw e002c01c\0" \
627"diuerr=md e002c014 1\0" \
628"pmregs=md e00e1000 2b\0" \
629"lawregs=md e0000c08 4b\0" \
630"lbcregs=md e0005000 36\0" \
631"dma0regs=md e0021100 12\0" \
632"dma1regs=md e0021180 12\0" \
633"dma2regs=md e0021200 12\0" \
634"dma3regs=md e0021280 12\0" \
635 PCI_ENV \
636 PCIE_ENV \
637 DMA_ENV
638#else
639#define CONFIG_EXTRA_ENV_SETTINGS \
640 "netdev=eth0\0" \
641 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
642 "consoledev=ttyS0\0" \
643 "ramdiskaddr=2000000\0" \
644 "ramdiskfile=8610hpcd/ramdisk.uboot\0" \
645 "fdtaddr=c00000\0" \
646 "fdtfile=8610hpcd/mpc8610_hpcd.dtb\0" \
647 "bdev=sda3\0"
648#endif
649
650#define CONFIG_NFSBOOTCOMMAND \
651 "setenv bootargs root=/dev/nfs rw " \
652 "nfsroot=$serverip:$rootpath " \
653 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
654 "console=$consoledev,$baudrate $othbootargs;" \
655 "tftp $loadaddr $bootfile;" \
656 "tftp $fdtaddr $fdtfile;" \
657 "bootm $loadaddr - $fdtaddr"
658
659#define CONFIG_RAMBOOTCOMMAND \
660 "setenv bootargs root=/dev/ram rw " \
661 "console=$consoledev,$baudrate $othbootargs;" \
662 "tftp $ramdiskaddr $ramdiskfile;" \
663 "tftp $loadaddr $bootfile;" \
664 "tftp $fdtaddr $fdtfile;" \
665 "bootm $loadaddr $ramdiskaddr $fdtaddr"
666
667#define CONFIG_BOOTCOMMAND \
668 "setenv bootargs root=/dev/$bdev rw " \
669 "console=$consoledev,$baudrate $othbootargs;" \
670 "tftp $loadaddr $bootfile;" \
671 "tftp $fdtaddr $fdtfile;" \
672 "bootm $loadaddr - $fdtaddr"
673
674#endif
675