1/* 2 * (C) Copyright 2000-2014 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8/* 9 * board/config.h - configuration options, board specific 10 */ 11 12#ifndef __CONFIG_H 13#define __CONFIG_H 14 15/* 16 * High Level Configuration Options 17 * (easy to change) 18 */ 19 20#define CONFIG_MPC850 1 /* This is a MPC850 CPU */ 21#define CONFIG_TQM850L 1 /* ...on a TQM8xxL module */ 22#define CONFIG_SYS_GENERIC_BOARD 23#define CONFIG_DISPLAY_BOARDINFO 24 25#define CONFIG_SYS_TEXT_BASE 0x40000000 26 27#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 28#define CONFIG_SYS_SMC_RXBUFLEN 128 29#define CONFIG_SYS_MAXIDLE 10 30#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 31 32#define CONFIG_BOOTCOUNT_LIMIT 33 34#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 35 36#define CONFIG_BOARD_TYPES 1 /* support board types */ 37 38#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" 39 40#undef CONFIG_BOOTARGS 41 42#define CONFIG_EXTRA_ENV_SETTINGS \ 43 "netdev=eth0\0" \ 44 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 45 "nfsroot=${serverip}:${rootpath}\0" \ 46 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 47 "addip=setenv bootargs ${bootargs} " \ 48 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 49 ":${hostname}:${netdev}:off panic=1\0" \ 50 "flash_nfs=run nfsargs addip;" \ 51 "bootm ${kernel_addr}\0" \ 52 "flash_self=run ramargs addip;" \ 53 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 54 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 55 "rootpath=/opt/eldk/ppc_8xx\0" \ 56 "hostname=TQM850L\0" \ 57 "bootfile=TQM850L/uImage\0" \ 58 "fdt_addr=40040000\0" \ 59 "kernel_addr=40060000\0" \ 60 "ramdisk_addr=40200000\0" \ 61 "u-boot=TQM850L/u-image.bin\0" \ 62 "load=tftp 200000 ${u-boot}\0" \ 63 "update=prot off 40000000 +${filesize};" \ 64 "era 40000000 +${filesize};" \ 65 "cp.b 200000 40000000 ${filesize};" \ 66 "sete filesize;save\0" \ 67 "" 68#define CONFIG_BOOTCOMMAND "run flash_self" 69 70#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 71#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 72 73#undef CONFIG_WATCHDOG /* watchdog disabled */ 74 75#define CONFIG_STATUS_LED 1 /* Status LED enabled */ 76 77#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 78 79/* 80 * BOOTP options 81 */ 82#define CONFIG_BOOTP_SUBNETMASK 83#define CONFIG_BOOTP_GATEWAY 84#define CONFIG_BOOTP_HOSTNAME 85#define CONFIG_BOOTP_BOOTPATH 86#define CONFIG_BOOTP_BOOTFILESIZE 87 88 89#define CONFIG_MAC_PARTITION 90#define CONFIG_DOS_PARTITION 91 92#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ 93 94/* 95 * Command line configuration. 96 */ 97#include <config_cmd_default.h> 98 99#define CONFIG_CMD_ASKENV 100#define CONFIG_CMD_DATE 101#define CONFIG_CMD_DHCP 102#define CONFIG_CMD_ELF 103#define CONFIG_CMD_EXT2 104#define CONFIG_CMD_IDE 105#define CONFIG_CMD_JFFS2 106#define CONFIG_CMD_NFS 107#define CONFIG_CMD_SNTP 108 109 110#define CONFIG_NETCONSOLE 111 112/* 113 * Miscellaneous configurable options 114 */ 115#define CONFIG_SYS_LONGHELP /* undef to save memory */ 116 117#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 118#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ 119 120#if defined(CONFIG_CMD_KGDB) 121#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 122#else 123#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 124#endif 125#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 126#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 127#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 128 129#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ 130#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ 131 132#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 133 134/* 135 * Low Level Configuration Settings 136 * (address mappings, register initial values, etc.) 137 * You should know what you are doing if you make changes here. 138 */ 139/*----------------------------------------------------------------------- 140 * Internal Memory Mapped Register 141 */ 142#define CONFIG_SYS_IMMR 0xFFF00000 143 144/*----------------------------------------------------------------------- 145 * Definitions for initial stack pointer and data area (in DPRAM) 146 */ 147#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 148#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 149#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 150#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 151 152/*----------------------------------------------------------------------- 153 * Start addresses for the final memory configuration 154 * (Set up by the startup code) 155 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 156 */ 157#define CONFIG_SYS_SDRAM_BASE 0x00000000 158#define CONFIG_SYS_FLASH_BASE 0x40000000 159#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 160#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 161#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ 162 163/* 164 * For booting Linux, the board info and command line data 165 * have to be in the first 8 MB of memory, since this is 166 * the maximum mapped by the Linux kernel during initialization. 167 */ 168#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 169 170/*----------------------------------------------------------------------- 171 * FLASH organization 172 */ 173 174/* use CFI flash driver */ 175#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 176#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 177#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE+flash_info[0].size } 178#define CONFIG_SYS_FLASH_EMPTY_INFO 179#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 180#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ 181#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ 182 183#define CONFIG_ENV_IS_IN_FLASH 1 184#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ 185#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ 186 187/* Address and size of Redundant Environment Sector */ 188#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) 189#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 190 191#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */ 192 193#define CONFIG_MISC_INIT_R /* Make sure to remap flashes correctly */ 194 195/*----------------------------------------------------------------------- 196 * Dynamic MTD partition support 197 */ 198#define CONFIG_CMD_MTDPARTS 199#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ 200#define CONFIG_FLASH_CFI_MTD 201#define MTDIDS_DEFAULT "nor0=TQM8xxL-0" 202 203#define MTDPARTS_DEFAULT "mtdparts=TQM8xxL-0:256k(u-boot)," \ 204 "128k(dtb)," \ 205 "1664k(kernel)," \ 206 "2m(rootfs)," \ 207 "4m(data)" 208 209/*----------------------------------------------------------------------- 210 * Hardware Information Block 211 */ 212#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 213#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 214#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 215 216/*----------------------------------------------------------------------- 217 * Cache Configuration 218 */ 219#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 220#if defined(CONFIG_CMD_KGDB) 221#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 222#endif 223 224/*----------------------------------------------------------------------- 225 * SYPCR - System Protection Control 11-9 226 * SYPCR can only be written once after reset! 227 *----------------------------------------------------------------------- 228 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 229 */ 230#if defined(CONFIG_WATCHDOG) 231#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 232 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 233#else 234#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 235#endif 236 237/*----------------------------------------------------------------------- 238 * SIUMCR - SIU Module Configuration 11-6 239 *----------------------------------------------------------------------- 240 * PCMCIA config., multi-function pin tri-state 241 */ 242#ifndef CONFIG_CAN_DRIVER 243#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 244#else /* we must activate GPL5 in the SIUMCR for CAN */ 245#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 246#endif /* CONFIG_CAN_DRIVER */ 247 248/*----------------------------------------------------------------------- 249 * TBSCR - Time Base Status and Control 11-26 250 *----------------------------------------------------------------------- 251 * Clear Reference Interrupt Status, Timebase freezing enabled 252 */ 253#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 254 255/*----------------------------------------------------------------------- 256 * RTCSC - Real-Time Clock Status and Control Register 11-27 257 *----------------------------------------------------------------------- 258 */ 259#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) 260 261/*----------------------------------------------------------------------- 262 * PISCR - Periodic Interrupt Status and Control 11-31 263 *----------------------------------------------------------------------- 264 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 265 */ 266#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 267 268/*----------------------------------------------------------------------- 269 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 270 *----------------------------------------------------------------------- 271 * Reset PLL lock status sticky bit, timer expired status bit and timer 272 * interrupt status bit 273 */ 274#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) 275 276/*----------------------------------------------------------------------- 277 * SCCR - System Clock and reset Control Register 15-27 278 *----------------------------------------------------------------------- 279 * Set clock output, timebase and RTC source and divider, 280 * power management and some other internal clocks 281 */ 282#define SCCR_MASK SCCR_EBDF11 283#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 284 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 285 SCCR_DFALCD00) 286 287/*----------------------------------------------------------------------- 288 * PCMCIA stuff 289 *----------------------------------------------------------------------- 290 * 291 */ 292#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 293#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 294#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 295#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 296#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 297#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 298#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 299#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 300 301/*----------------------------------------------------------------------- 302 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 303 *----------------------------------------------------------------------- 304 */ 305 306#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ 307#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 308 309#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 310#undef CONFIG_IDE_LED /* LED for ide not supported */ 311#undef CONFIG_IDE_RESET /* reset for ide not supported */ 312 313#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 314#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 315 316#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 317 318#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 319 320/* Offset for data I/O */ 321#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 322 323/* Offset for normal register accesses */ 324#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 325 326/* Offset for alternate registers */ 327#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 328 329/*----------------------------------------------------------------------- 330 * 331 *----------------------------------------------------------------------- 332 * 333 */ 334#define CONFIG_SYS_DER 0 335 336/* 337 * Init Memory Controller: 338 * 339 * BR0/1 and OR0/1 (FLASH) 340 */ 341 342#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 343#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 344 345/* used to re-map FLASH both when starting from SRAM or FLASH: 346 * restrict access enough to keep SRAM working (if any) 347 * but not too much to meddle with FLASH accesses 348 */ 349#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 350#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 351 352/* 353 * FLASH timing: 354 */ 355#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ 356 OR_SCY_3_CLK | OR_EHTR | OR_BI) 357 358#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 359#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 360#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 361 362#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 363#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 364#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 365 366/* 367 * BR2/3 and OR2/3 (SDRAM) 368 * 369 */ 370#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 371#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 372#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ 373 374/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 375#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 376 377#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 378#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 379 380#ifndef CONFIG_CAN_DRIVER 381#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 382#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 383#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 384#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 385#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 386#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 387#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 388 BR_PS_8 | BR_MS_UPMB | BR_V ) 389#endif /* CONFIG_CAN_DRIVER */ 390 391/* 392 * Memory Periodic Timer Prescaler 393 * 394 * The Divider for PTA (refresh timer) configuration is based on an 395 * example SDRAM configuration (64 MBit, one bank). The adjustment to 396 * the number of chip selects (NCS) and the actually needed refresh 397 * rate is done by setting MPTPR. 398 * 399 * PTA is calculated from 400 * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) 401 * 402 * gclk CPU clock (not bus clock!) 403 * Trefresh Refresh cycle * 4 (four word bursts used) 404 * 405 * 4096 Rows from SDRAM example configuration 406 * 1000 factor s -> ms 407 * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration 408 * 4 Number of refresh cycles per period 409 * 64 Refresh cycle in ms per number of rows 410 * -------------------------------------------- 411 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 412 * 413 * 50 MHz => 50.000.000 / Divider = 98 414 * 66 Mhz => 66.000.000 / Divider = 129 415 * 80 Mhz => 80.000.000 / Divider = 156 416 */ 417 418#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) 419#define CONFIG_SYS_MAMR_PTA 98 420 421/* 422 * For 16 MBit, refresh rates could be 31.3 us 423 * (= 64 ms / 2K = 125 / quad bursts). 424 * For a simpler initialization, 15.6 us is used instead. 425 * 426 * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks 427 * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank 428 */ 429#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ 430#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ 431 432/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ 433#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ 434#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ 435 436/* 437 * MAMR settings for SDRAM 438 */ 439 440/* 8 column SDRAM */ 441#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 442 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 443 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 444/* 9 column SDRAM */ 445#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 446 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 447 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 448 449/* pass open firmware flat tree */ 450#define CONFIG_OF_LIBFDT 1 451#define CONFIG_OF_BOARD_SETUP 1 452#define CONFIG_HWCONFIG 1 453 454#endif /* __CONFIG_H */ 455