1/* 2 * (C) Copyright 2000-2014 3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. 4 * 5 * (C) Copyright 2006 6 * Martin Krause, TQ-Systems GmBH, martin.krause@tqs.de 7 * 8 * SPDX-License-Identifier: GPL-2.0+ 9 */ 10 11/* 12 * board/config.h - configuration options, board specific 13 */ 14 15#ifndef __CONFIG_H 16#define __CONFIG_H 17 18/* 19 * High Level Configuration Options 20 * (easy to change) 21 */ 22 23#define CONFIG_MPC885 1 /* This is a MPC885 CPU */ 24#define CONFIG_TQM885D 1 /* ...on a TQM88D module */ 25#define CONFIG_SYS_GENERIC_BOARD 26#define CONFIG_DISPLAY_BOARDINFO 27 28#define CONFIG_SYS_TEXT_BASE 0x40000000 29 30#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ 31#define CONFIG_SYS_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ 32#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ 33#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */ 34 /* (it will be used if there is no */ 35 /* 'cpuclk' variable with valid value) */ 36 37#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ 38#define CONFIG_SYS_SMC_RXBUFLEN 128 39#define CONFIG_SYS_MAXIDLE 10 40#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ 41 42#define CONFIG_BOOTCOUNT_LIMIT 43 44#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ 45 46#define CONFIG_BOARD_TYPES 1 /* support board types */ 47 48#define CONFIG_PREBOOT "echo;" \ 49 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ 50 "echo" 51 52#undef CONFIG_BOOTARGS 53 54#define CONFIG_EXTRA_ENV_SETTINGS \ 55 "netdev=eth0\0" \ 56 "nfsargs=setenv bootargs root=/dev/nfs rw " \ 57 "nfsroot=${serverip}:${rootpath}\0" \ 58 "ramargs=setenv bootargs root=/dev/ram rw\0" \ 59 "addip=setenv bootargs ${bootargs} " \ 60 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ 61 ":${hostname}:${netdev}:off panic=1\0" \ 62 "flash_nfs=run nfsargs addip;" \ 63 "bootm ${kernel_addr}\0" \ 64 "flash_self=run ramargs addip;" \ 65 "bootm ${kernel_addr} ${ramdisk_addr}\0" \ 66 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ 67 "rootpath=/opt/eldk/ppc_8xx\0" \ 68 "bootfile=/tftpboot/TQM885D/uImage\0" \ 69 "fdt_addr=400C0000\0" \ 70 "kernel_addr=40100000\0" \ 71 "ramdisk_addr=40280000\0" \ 72 "load=tftp 200000 ${u-boot}\0" \ 73 "update=protect off 40000000 +${filesize};" \ 74 "erase 40000000 +${filesize};" \ 75 "cp.b 200000 40000000 ${filesize};" \ 76 "protect on 40000000 +${filesize}\0" \ 77 "" 78#define CONFIG_BOOTCOMMAND "run flash_self" 79 80#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ 81#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ 82 83#undef CONFIG_WATCHDOG /* watchdog disabled */ 84 85#define CONFIG_STATUS_LED 1 /* Status LED enabled */ 86 87#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ 88 89/* enable I2C and select the hardware/software driver */ 90#define CONFIG_SYS_I2C 91#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ 92#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */ 93#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE 94/* 95 * Software (bit-bang) I2C driver configuration 96 */ 97#define PB_SCL 0x00000020 /* PB 26 */ 98#define PB_SDA 0x00000010 /* PB 27 */ 99 100#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) 101#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) 102#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) 103#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) 104#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ 105 else immr->im_cpm.cp_pbdat &= ~PB_SDA 106#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ 107 else immr->im_cpm.cp_pbdat &= ~PB_SCL 108#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ 109 110#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */ 111#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ 112#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 113#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ 114 115# define CONFIG_RTC_DS1337 1 116# define CONFIG_SYS_I2C_RTC_ADDR 0x68 117 118/* 119 * BOOTP options 120 */ 121#define CONFIG_BOOTP_SUBNETMASK 122#define CONFIG_BOOTP_GATEWAY 123#define CONFIG_BOOTP_HOSTNAME 124#define CONFIG_BOOTP_BOOTPATH 125#define CONFIG_BOOTP_BOOTFILESIZE 126 127 128#define CONFIG_MAC_PARTITION 129#define CONFIG_DOS_PARTITION 130 131#undef CONFIG_RTC_MPC8xx /* MPC885 does not support RTC */ 132 133#define CONFIG_TIMESTAMP /* but print image timestmps */ 134 135 136/* 137 * Command line configuration. 138 */ 139#include <config_cmd_default.h> 140 141#define CONFIG_CMD_ASKENV 142#define CONFIG_CMD_DATE 143#define CONFIG_CMD_DHCP 144#define CONFIG_CMD_EEPROM 145#define CONFIG_CMD_EXT2 146#define CONFIG_CMD_I2C 147#define CONFIG_CMD_IDE 148#define CONFIG_CMD_MII 149#define CONFIG_CMD_NFS 150#define CONFIG_CMD_PING 151 152 153/* 154 * Miscellaneous configurable options 155 */ 156#define CONFIG_SYS_LONGHELP /* undef to save memory */ 157 158#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ 159#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ 160 161#if defined(CONFIG_CMD_KGDB) 162#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ 163#else 164#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ 165#endif 166#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ 167#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ 168#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ 169 170#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ 171#define CONFIG_SYS_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */ 172#define CONFIG_SYS_ALT_MEMTEST /* alternate, more extensive 173 memory test.*/ 174 175#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ 176 177/* 178 * Enable loopw command. 179 */ 180#define CONFIG_LOOPW 181 182/* 183 * Low Level Configuration Settings 184 * (address mappings, register initial values, etc.) 185 * You should know what you are doing if you make changes here. 186 */ 187/*----------------------------------------------------------------------- 188 * Internal Memory Mapped Register 189 */ 190#define CONFIG_SYS_IMMR 0xFFF00000 191 192/*----------------------------------------------------------------------- 193 * Definitions for initial stack pointer and data area (in DPRAM) 194 */ 195#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR 196#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ 197#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) 198#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET 199 200/*----------------------------------------------------------------------- 201 * Start addresses for the final memory configuration 202 * (Set up by the startup code) 203 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 204 */ 205#define CONFIG_SYS_SDRAM_BASE 0x00000000 206#define CONFIG_SYS_FLASH_BASE 0x40000000 207#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ 208#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE 209#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */ 210 211/* 212 * For booting Linux, the board info and command line data 213 * have to be in the first 8 MB of memory, since this is 214 * the maximum mapped by the Linux kernel during initialization. 215 */ 216#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ 217 218/*----------------------------------------------------------------------- 219 * FLASH organization 220 */ 221 222/* use CFI flash driver */ 223#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ 224#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ 225#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } 226#define CONFIG_SYS_FLASH_EMPTY_INFO 227#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 228#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ 229#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ 230 231#define CONFIG_ENV_IS_IN_FLASH 1 232#define CONFIG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ 233#define CONFIG_ENV_SIZE 0x08000 /* Total Size of Environment */ 234#define CONFIG_ENV_SECT_SIZE 0x40000 /* Total Size of Environment Sector */ 235 236/* Address and size of Redundant Environment Sector */ 237#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE) 238#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) 239 240/*----------------------------------------------------------------------- 241 * Hardware Information Block 242 */ 243#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ 244#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ 245#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ 246 247/*----------------------------------------------------------------------- 248 * Cache Configuration 249 */ 250#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ 251#if defined(CONFIG_CMD_KGDB) 252#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ 253#endif 254 255/*----------------------------------------------------------------------- 256 * SYPCR - System Protection Control 11-9 257 * SYPCR can only be written once after reset! 258 *----------------------------------------------------------------------- 259 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze 260 */ 261#if defined(CONFIG_WATCHDOG) 262#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ 263 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) 264#else 265#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) 266#endif 267 268/*----------------------------------------------------------------------- 269 * SIUMCR - SIU Module Configuration 11-6 270 *----------------------------------------------------------------------- 271 * PCMCIA config., multi-function pin tri-state 272 */ 273#ifndef CONFIG_CAN_DRIVER 274#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 275#else /* we must activate GPL5 in the SIUMCR for CAN */ 276#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) 277#endif /* CONFIG_CAN_DRIVER */ 278 279/*----------------------------------------------------------------------- 280 * TBSCR - Time Base Status and Control 11-26 281 *----------------------------------------------------------------------- 282 * Clear Reference Interrupt Status, Timebase freezing enabled 283 */ 284#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) 285 286/*----------------------------------------------------------------------- 287 * PISCR - Periodic Interrupt Status and Control 11-31 288 *----------------------------------------------------------------------- 289 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled 290 */ 291#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) 292 293/*----------------------------------------------------------------------- 294 * SCCR - System Clock and reset Control Register 15-27 295 *----------------------------------------------------------------------- 296 * Set clock output, timebase and RTC source and divider, 297 * power management and some other internal clocks 298 */ 299#define SCCR_MASK SCCR_EBDF11 300#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ 301 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ 302 SCCR_DFALCD00) 303 304/*----------------------------------------------------------------------- 305 * PCMCIA stuff 306 *----------------------------------------------------------------------- 307 * 308 */ 309#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) 310#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) 311#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) 312#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) 313#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) 314#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) 315#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) 316#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) 317 318/*----------------------------------------------------------------------- 319 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) 320 *----------------------------------------------------------------------- 321 */ 322 323#define CONFIG_IDE_PREINIT 1 /* Use preinit IDE hook */ 324#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ 325 326#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ 327#undef CONFIG_IDE_LED /* LED for ide not supported */ 328#undef CONFIG_IDE_RESET /* reset for ide not supported */ 329 330#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ 331#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ 332 333#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 334 335#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR 336 337/* Offset for data I/O */ 338#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 339 340/* Offset for normal register accesses */ 341#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) 342 343/* Offset for alternate registers */ 344#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 345 346/*----------------------------------------------------------------------- 347 * 348 *----------------------------------------------------------------------- 349 * 350 */ 351#define CONFIG_SYS_DER 0 352 353/* 354 * Init Memory Controller: 355 * 356 * BR0/1 and OR0/1 (FLASH) 357 */ 358 359#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ 360#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ 361 362/* used to re-map FLASH both when starting from SRAM or FLASH: 363 * restrict access enough to keep SRAM working (if any) 364 * but not too much to meddle with FLASH accesses 365 */ 366#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ 367#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ 368 369/* 370 * FLASH timing: Default value of OR0 after reset 371 */ 372#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ 373 OR_SCY_6_CLK | OR_TRLX) 374 375#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 376#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) 377#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) 378 379#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP 380#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM 381#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) 382 383/* 384 * BR2/3 and OR2/3 (SDRAM) 385 * 386 */ 387#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ 388#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ 389#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */ 390 391/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ 392#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 393 394#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) 395#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 396 397#ifndef CONFIG_CAN_DRIVER 398#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM 399#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) 400#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ 401#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ 402#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ 403#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) 404#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ 405 BR_PS_8 | BR_MS_UPMB | BR_V ) 406#endif /* CONFIG_CAN_DRIVER */ 407 408/* 409 * 4096 Rows from SDRAM example configuration 410 * 1000 factor s -> ms 411 * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration 412 * 4 Number of refresh cycles per period 413 * 64 Refresh cycle in ms per number of rows 414 */ 415#define CONFIG_SYS_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) 416 417/* 418 * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad) 419 * 420 * CPUclock(MHz) * 31.2 421 * CONFIG_SYS_MAMR_PTA = ----------------------------------- with DFBRG = 0 422 * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16 423 * 424 * CPU clock = 15 MHz: CONFIG_SYS_MAMR_PTA = 29 -> 4 * 7.73 us 425 * CPU clock = 50 MHz: CONFIG_SYS_MAMR_PTA = 97 -> 4 * 7.76 us 426 * CPU clock = 66 MHz: CONFIG_SYS_MAMR_PTA = 128 -> 4 * 7.75 us 427 * CPU clock = 133 MHz: CONFIG_SYS_MAMR_PTA = 255 -> 4 * 7.67 us 428 * 429 * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will 430 * be met also in the default configuration, i.e. if environment variable 431 * 'cpuclk' is not set. 432 */ 433#define CONFIG_SYS_MAMR_PTA 128 434 435/* 436 * Memory Periodic Timer Prescaler Register (MPTPR) values. 437 */ 438/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */ 439#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 440/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */ 441#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 442 443/* 444 * MAMR settings for SDRAM 445 */ 446 447/* 8 column SDRAM */ 448#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 449 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ 450 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 451/* 9 column SDRAM */ 452#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 453 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ 454 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 455/* 10 column SDRAM */ 456#define CONFIG_SYS_MAMR_10COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ 457 MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ 458 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) 459 460/* 461 * Network configuration 462 */ 463#define CONFIG_SCC2_ENET /* enable ethernet on SCC2 */ 464#define CONFIG_FEC_ENET /* enable ethernet on FEC */ 465#define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */ 466#define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */ 467 468#if defined(CONFIG_CMD_MII) 469#define CONFIG_SYS_DISCOVER_PHY 470#define CONFIG_MII_INIT 1 471#endif 472 473#define CONFIG_NET_RETRY_COUNT 1 /* reduce max. timeout before 474 switching to another netwok (if the 475 tried network is unreachable) */ 476 477#define CONFIG_ETHPRIME "SCC" 478 479/* pass open firmware flat tree */ 480#define CONFIG_OF_LIBFDT 1 481#define CONFIG_OF_BOARD_SETUP 1 482#define CONFIG_HWCONFIG 1 483 484#endif /* __CONFIG_H */ 485