1
2
3
4
5
6
7
8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11#define CONFIG_405EP 1
12#define CONFIG_IO 1
13
14#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
15
16
17
18
19#define CONFIG_HOSTNAME io
20#define CONFIG_IDENT_STRING " io 0.06"
21#include "amcc-common.h"
22
23#define CONFIG_BOARD_EARLY_INIT_F
24#define CONFIG_BOARD_EARLY_INIT_R
25#define CONFIG_MISC_INIT_R
26#define CONFIG_LAST_STAGE_INIT
27#define CONFIG_SYS_GENERIC_BOARD
28
29#define CONFIG_SYS_CLK_FREQ 33333333
30
31
32
33
34#define PLLMR0_DEFAULT PLLMR0_266_133_66
35#define PLLMR1_DEFAULT PLLMR1_266_133_66
36
37#undef CONFIG_ZERO_BOOTDELAY_CHECK
38#define CONFIG_AUTOBOOT_KEYED
39#define CONFIG_AUTOBOOT_STOP_STR " "
40
41
42#define CONFIG_FIT
43#define CONFIG_FIT_VERBOSE
44#define CONFIG_FIT_DISABLE_SHA256
45
46#define CONFIG_ENV_IS_IN_FLASH
47
48
49
50
51#define CONFIG_EXTRA_ENV_SETTINGS \
52 CONFIG_AMCC_DEF_ENV \
53 CONFIG_AMCC_DEF_ENV_POWERPC \
54 CONFIG_AMCC_DEF_ENV_NOR_UPD \
55 "kernel_addr=fc000000\0" \
56 "fdt_addr=fc1e0000\0" \
57 "ramdisk_addr=fc200000\0" \
58 ""
59
60#define CONFIG_PHY_ADDR 4
61#define CONFIG_HAS_ETH0
62#define CONFIG_HAS_ETH1
63#define CONFIG_PHY1_ADDR 0xc
64#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
65
66
67
68
69#define CONFIG_CMD_DTT
70#undef CONFIG_CMD_DHCP
71#undef CONFIG_CMD_DIAG
72#undef CONFIG_CMD_EEPROM
73#undef CONFIG_CMD_ELF
74#undef CONFIG_CMD_I2C
75#undef CONFIG_CMD_IRQ
76#undef CONFIG_CMD_NFS
77
78
79
80
81#define CONFIG_SDRAM_BANK0 1
82
83
84#define CONFIG_SYS_SDRAM_CL 3
85#define CONFIG_SYS_SDRAM_tRP 20
86#define CONFIG_SYS_SDRAM_tRC 66
87#define CONFIG_SYS_SDRAM_tRCD 20
88#define CONFIG_SYS_SDRAM_tRFC 66
89
90
91
92
93
94
95
96
97
98
99#define CONFIG_CONS_INDEX 1
100#undef CONFIG_SYS_EXT_SERIAL_CLOCK
101#undef CONFIG_SYS_405_UART_ERRATA_59
102#define CONFIG_SYS_BASE_BAUD 691200
103
104
105
106
107#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
108
109
110#define CONFIG_DTT_LM63 1
111#define CONFIG_DTT_SENSORS { 0 }
112#define CONFIG_DTT_PWM_LOOKUPTABLE \
113 { { 40, 10 }, { 50, 20 }, { 60, 40 } }
114#define CONFIG_DTT_TACH_LIMIT 0xa10
115
116
117
118
119#define CONFIG_SYS_FLASH_CFI
120#define CONFIG_FLASH_CFI_DRIVER
121
122#define CONFIG_SYS_FLASH_BASE 0xFC000000
123#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
124
125#define CONFIG_SYS_MAX_FLASH_BANKS 1
126#define CONFIG_SYS_MAX_FLASH_SECT 512
127
128#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
129#define CONFIG_SYS_FLASH_WRITE_TOUT 500
130
131#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
132
133#define CONFIG_SYS_FLASH_EMPTY_INFO
134#define CONFIG_SYS_FLASH_QUIET_TEST 1
135
136#ifdef CONFIG_ENV_IS_IN_FLASH
137#define CONFIG_ENV_SECT_SIZE 0x20000
138#define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
139#define CONFIG_ENV_SIZE 0x2000
140
141
142#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
143#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
144#endif
145
146
147#define CONFIG_BITBANGMII
148#define CONFIG_BITBANGMII_MULTI
149
150#define CONFIG_SYS_MDIO_PIN (0x80000000 >> 13)
151#define CONFIG_SYS_MDC_PIN (0x80000000 >> 7)
152
153#define CONFIG_SYS_GBIT_MII_BUSNAME "io_miiphy"
154
155
156
157
158#define CONFIG_SYS_4xx_GPIO_TABLE { \
159{ \
160 \
161{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
162{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
163{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
164{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
165{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
166{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, \
167{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
168{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, \
169{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
170{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
171{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
172{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
173{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
174{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
175{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
176{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
177{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
178{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
179{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
180{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
181{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
182{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
183{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
184{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
185{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
186{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
187{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
188{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
189{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
190{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
191{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
192{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
193} \
194}
195
196
197
198
199
200#define CONFIG_SYS_TEMP_STACK_OCM 1
201
202
203#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
204#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
205#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
206#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE
207
208#define CONFIG_SYS_GBL_DATA_OFFSET \
209 (CONFIG_SYS_INIT_RAM_END - GENERATED_GBL_DATA_SIZE)
210#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
211
212
213
214
215
216
217#define CONFIG_SYS_EBC_PB0AP 0xa382a880
218
219#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000
220
221
222#define CONFIG_SYS_EBC_PB1AP 0x92015480
223
224#define CONFIG_SYS_EBC_PB1CR 0x7f318000
225
226
227#define CONFIG_SYS_FPGA0_BASE 0x7f100000
228#define CONFIG_SYS_EBC_PB2AP 0x02025080
229
230#define CONFIG_SYS_EBC_PB2CR 0x7f11a000
231
232#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
233#define CONFIG_SYS_FPGA_DONE(k) 0x0010
234
235#define CONFIG_SYS_FPGA_COUNT 1
236
237#define CONFIG_SYS_FPGA_PTR \
238 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }
239
240#define CONFIG_SYS_FPGA_COMMON
241
242
243#define CONFIG_SYS_LATCH_BASE 0x7f200000
244#define CONFIG_SYS_EBC_PB3AP 0xa2015480
245
246#define CONFIG_SYS_EBC_PB3CR 0x7f21a000
247
248#define CONFIG_SYS_LATCH0_RESET 0xffff
249#define CONFIG_SYS_LATCH0_BOOT 0xffff
250#define CONFIG_SYS_LATCH1_RESET 0xffbf
251#define CONFIG_SYS_LATCH1_BOOT 0xffff
252
253#endif
254