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8#ifndef __CONFIG_H
9#define __CONFIG_H
10
11
12#define CONFIG_405EP 1
13#define CONFIG_NEO 1
14
15#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
16
17
18
19
20#define CONFIG_HOSTNAME neo
21#define CONFIG_IDENT_STRING " neo 0.02"
22#include "amcc-common.h"
23
24#define CONFIG_BOARD_EARLY_INIT_F
25#define CONFIG_BOARD_EARLY_INIT_R
26#define CONFIG_MISC_INIT_R
27#define CONFIG_LAST_STAGE_INIT
28#define CONFIG_SYS_GENERIC_BOARD
29
30#define CONFIG_SYS_CLK_FREQ 33333333
31
32
33
34
35#define PLLMR0_DEFAULT PLLMR0_266_133_66_33
36#define PLLMR1_DEFAULT PLLMR1_266_133_66_33
37
38
39#define CONFIG_FIT
40#define CONFIG_FIT_VERBOSE
41#define CONFIG_FIT_DISABLE_SHA256
42
43#define CONFIG_ENV_IS_IN_FLASH
44
45
46
47
48#define CONFIG_EXTRA_ENV_SETTINGS \
49 CONFIG_AMCC_DEF_ENV \
50 CONFIG_AMCC_DEF_ENV_POWERPC \
51 CONFIG_AMCC_DEF_ENV_NOR_UPD \
52 "kernel_addr=fc000000\0" \
53 "fdt_addr=fc1e0000\0" \
54 "ramdisk_addr=fc200000\0" \
55 ""
56
57#define CONFIG_PHY_ADDR 4
58#define CONFIG_HAS_ETH0
59#define CONFIG_HAS_ETH1
60#define CONFIG_PHY1_ADDR 0xc
61#define CONFIG_PHY_CLK_FREQ EMAC_STACR_CLK_66MHZ
62
63
64
65
66#define CONFIG_CMD_DTT
67#undef CONFIG_CMD_DHCP
68#undef CONFIG_CMD_DIAG
69#undef CONFIG_CMD_EEPROM
70#undef CONFIG_CMD_ELF
71#undef CONFIG_CMD_I2C
72#undef CONFIG_CMD_IRQ
73#undef CONFIG_CMD_NFS
74
75
76
77
78#define CONFIG_SDRAM_BANK0 1
79
80
81#define CONFIG_SYS_SDRAM_CL 3
82#define CONFIG_SYS_SDRAM_tRP 20
83#define CONFIG_SYS_SDRAM_tRC 66
84#define CONFIG_SYS_SDRAM_tRCD 20
85#define CONFIG_SYS_SDRAM_tRFC 66
86
87
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90
91
92
93
94
95
96#define CONFIG_CONS_INDEX 1
97#define CONFIG_SYS_NS16550
98#define CONFIG_SYS_NS16550_SERIAL
99#define CONFIG_SYS_NS16550_REG_SIZE 1
100#define CONFIG_SYS_NS16550_CLK get_serial_clock()
101
102#undef CONFIG_SYS_EXT_SERIAL_CLOCK
103#undef CONFIG_SYS_405_UART_ERRATA_59
104#define CONFIG_SYS_BASE_BAUD 691200
105
106
107
108
109#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000
110
111
112#define CONFIG_RTC_DS1337
113#define CONFIG_SYS_I2C_RTC_ADDR 0x68
114
115
116#define CONFIG_DTT_LM63 1
117#define CONFIG_DTT_SENSORS { 0 }
118#define CONFIG_DTT_PWM_LOOKUPTABLE \
119 { { 40, 10 }, { 50, 20 }, { 60, 40 } }
120#define CONFIG_DTT_TACH_LIMIT 0xa10
121
122
123
124
125#define CONFIG_SYS_FLASH_CFI
126#define CONFIG_FLASH_CFI_DRIVER
127
128#define CONFIG_SYS_FLASH_BASE 0xFC000000
129#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
130
131#define CONFIG_SYS_MAX_FLASH_BANKS 1
132#define CONFIG_SYS_MAX_FLASH_SECT 512
133
134#define CONFIG_SYS_FLASH_ERASE_TOUT 120000
135#define CONFIG_SYS_FLASH_WRITE_TOUT 500
136
137#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
138
139#define CONFIG_SYS_FLASH_EMPTY_INFO
140#define CONFIG_SYS_FLASH_QUIET_TEST 1
141
142#ifdef CONFIG_ENV_IS_IN_FLASH
143#define CONFIG_ENV_SECT_SIZE 0x20000
144#define CONFIG_ENV_ADDR 0xFFF00000
145#define CONFIG_ENV_SIZE 0x20000
146
147
148#define CONFIG_ENV_ADDR_REDUND 0xFFF20000
149#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
150#endif
151
152
153
154
155#define CONFIG_SYS_4xx_GPIO_TABLE { \
156{ \
157 \
158{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
159{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
160{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
161{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
162{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
163{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_1 }, \
164{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
165{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
166{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
167{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
168{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
169{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
170{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
171{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
172{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
173{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
174{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
175{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
176{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
177{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
178{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
179{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
180{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
181{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
182{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
183{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
184{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
185{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
186{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
187{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, \
188{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, \
189{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, \
190} \
191}
192
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194
195
196
197#define CONFIG_SYS_TEMP_STACK_OCM 1
198
199
200#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
201#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
202#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR
203#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE
204
205#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
206#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
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211
212
213#define CONFIG_SYS_EBC_PB0AP 0x92015480
214#define CONFIG_SYS_EBC_PB0CR 0xFC0DA000
215
216
217#define CONFIG_SYS_EBC_PB1AP 0x92015480
218#define CONFIG_SYS_EBC_PB1CR 0xFB85A000
219
220
221#define CONFIG_SYS_FPGA0_BASE 0x7f100000
222#define CONFIG_SYS_EBC_PB2AP 0x92015480
223#define CONFIG_SYS_EBC_PB2CR 0x7f11a000
224
225#define CONFIG_SYS_FPGA_BASE(k) CONFIG_SYS_FPGA0_BASE
226
227#define CONFIG_SYS_FPGA_COUNT 1
228
229#define CONFIG_SYS_FPGA_PTR \
230 { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE }
231
232#define CONFIG_SYS_FPGA_COMMON
233
234
235#define CONFIG_SYS_LATCH_BASE 0x7f200000
236#define CONFIG_SYS_EBC_PB3AP 0x92015480
237#define CONFIG_SYS_EBC_PB3CR 0x7f21a000
238
239#define CONFIG_SYS_LATCH0_RESET 0xffff
240#define CONFIG_SYS_LATCH0_BOOT 0xffff
241#define CONFIG_SYS_LATCH1_RESET 0xffbf
242#define CONFIG_SYS_LATCH1_BOOT 0xffff
243
244#endif
245