LXR uboot/include/configs/sequoia.h

   1/*
   2 * (C) Copyright 2006-2008
   3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4 *
   5 * (C) Copyright 2006
   6 * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
   7 * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
   8 *
   9 * SPDX-License-Identifier:     GPL-2.0+
  10 */
  11
  12/*
  13 * sequoia.h - configuration for Sequoia & Rainier boards
  14 */
  15#ifndef __CONFIG_H
  16#define __CONFIG_H
  17
  18/*
  19 * High Level Configuration Options
  20 */
  21/* This config file is used for Sequoia (440EPx) and Rainier (440GRx)   */
  22#ifndef CONFIG_RAINIER
  23#define CONFIG_440EPX           1       /* Specific PPC440EPx           */
  24#define CONFIG_HOSTNAME         sequoia
  25#else
  26#define CONFIG_440GRX           1       /* Specific PPC440GRx           */
  27#define CONFIG_HOSTNAME         rainier
  28#endif
  29#define CONFIG_440              1       /* ... PPC440 family            */
  30
  31#ifndef CONFIG_SYS_TEXT_BASE
  32#define CONFIG_SYS_TEXT_BASE    0xFFF80000
  33#endif
  34
  35/*
  36 * Include common defines/options for all AMCC eval boards
  37 */
  38#include "amcc-common.h"
  39
  40/* Detect Sequoia PLL input clock automatically via CPLD bit            */
  41#define CONFIG_SYS_CLK_FREQ    ((in8(CONFIG_SYS_BCSR_BASE + 3) & 0x80) ? \
  42                                33333333 : 33000000)
  43
  44/*
  45 * Define this if you want support for video console with radeon 9200 pci card
  46 * Also set CONFIG_SYS_TEXT_BASE to 0xFFF80000 in board/amcc/sequoia/config.mk in this case
  47 */
  48#undef CONFIG_VIDEO
  49
  50#ifdef CONFIG_VIDEO
  51/*
  52 * 44x dcache supported is working now on sequoia, but we don't enable
  53 * it yet since it needs further testing
  54 */
  55#define CONFIG_4xx_DCACHE               /* enable dcache                */
  56#endif
  57
  58#define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
  59#define CONFIG_MISC_INIT_R      1       /* Call misc_init_r             */
  60
  61/*
  62 * Base addresses -- Note these are effective addresses where the actual
  63 * resources get mapped (not physical addresses).
  64 */
  65#define CONFIG_SYS_TLB_FOR_BOOT_FLASH   0x0003
  66#define CONFIG_SYS_BOOT_BASE_ADDR       0xf0000000
  67#define CONFIG_SYS_FLASH_BASE           0xfc000000      /* start of FLASH       */
  68#define CONFIG_SYS_NAND_ADDR            0xd0000000      /* NAND Flash           */
  69#define CONFIG_SYS_OCM_BASE             0xe0010000      /* ocm                  */
  70#define CONFIG_SYS_OCM_DATA_ADDR        CONFIG_SYS_OCM_BASE
  71#define CONFIG_SYS_PCI_BASE             0xe0000000      /* Internal PCI regs    */
  72#define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped pci memory    */
  73#define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE  + 0x10000000
  74#define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
  75#define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
  76
  77#define CONFIG_SYS_USB2D0_BASE          0xe0000100
  78#define CONFIG_SYS_USB_DEVICE           0xe0000000
  79#define CONFIG_SYS_USB_HOST             0xe0000400
  80#define CONFIG_SYS_BCSR_BASE            0xc0000000
  81
  82/*
  83 * Initial RAM & stack pointer
  84 */
  85/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache     */
  86#define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_BASE     /* OCM                  */
  87#define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)
  88#define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  89#define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
  90
  91/*
  92 * Serial Port
  93 */
  94#define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  95#define CONFIG_SYS_EXT_SERIAL_CLOCK     11059200        /* ext. 11.059MHz clk   */
  96
  97/*
  98 * Environment
  99 */
 100#if defined(CONFIG_SYS_RAMBOOT)
 101#define CONFIG_ENV_IS_NOWHERE           /* Store env in memory only     */
 102#define CONFIG_ENV_SIZE         (8 << 10)
 103/*
 104 * In RAM-booting version, we have no environment storage. So we need to
 105 * provide at least preliminary MAC addresses for the 4xx EMAC driver to
 106 * register the interfaces. Those two addresses are generated via the
 107 * tools/gen_eth_addr tool and should only be used in a closed laboratory
 108 * environment.
 109 */
 110#define CONFIG_ETHADDR          4a:56:49:22:3e:43
 111#define CONFIG_ETH1ADDR         02:93:53:d5:06:98
 112#else
 113#define CONFIG_ENV_IS_IN_FLASH          /* use FLASH for environ vars   */
 114#endif
 115
 116#if defined(CONFIG_CMD_FLASH)
 117/*
 118 * FLASH related
 119 */
 120#define CONFIG_SYS_FLASH_CFI                    /* The flash is CFI compatible  */
 121#define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver        */
 122
 123#define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 124
 125#define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks         */
 126#define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip  */
 127
 128#define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)    */
 129#define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)    */
 130
 131#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)   */
 132#define CONFIG_SYS_FLASH_PROTECTION     1       /* use hardware flash protection      */
 133
 134#define CONFIG_SYS_FLASH_EMPTY_INFO           /* print 'E' for empty sector on flinfo */
 135#define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash      */
 136
 137#ifdef CONFIG_ENV_IS_IN_FLASH
 138#define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector        */
 139#define CONFIG_ENV_ADDR         ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 140#define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector   */
 141
 142/* Address and size of Redundant Environment Sector     */
 143#define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 144#define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 145#endif
 146#endif /* CONFIG_CMD_FLASH */
 147
 148/*
 149 * DDR SDRAM
 150 */
 151#define CONFIG_SYS_MBYTES_SDRAM        (256)    /* 256MB                        */
 152#if !defined(CONFIG_SYS_RAMBOOT)
 153#define CONFIG_DDR_DATA_EYE             /* use DDR2 optimization        */
 154#endif
 155#define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4kbytes     */
 156                                        /* 440EPx errata CHIP 11        */
 157
 158/*
 159 * I2C
 160 */
 161#define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 162
 163#define CONFIG_SYS_I2C_MULTI_EEPROMS
 164#define CONFIG_SYS_I2C_EEPROM_ADDR      (0xa8>>1)
 165#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 166#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 167#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 168
 169/* I2C bootstrap EEPROM */
 170#define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x52
 171#define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET     0
 172#define CONFIG_4xx_CONFIG_BLOCKSIZE             16
 173
 174/* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
 175#define CONFIG_DTT_LM75         1       /* ON Semi's LM75               */
 176#define CONFIG_DTT_AD7414       1       /* use AD7414                   */
 177#define CONFIG_DTT_SENSORS      {0}     /* Sensor addresses             */
 178#define CONFIG_SYS_DTT_MAX_TEMP 70
 179#define CONFIG_SYS_DTT_LOW_TEMP -30
 180#define CONFIG_SYS_DTT_HYSTERESIS       3
 181
 182/*
 183 * Default environment variables
 184 */
 185#define CONFIG_EXTRA_ENV_SETTINGS                                       \
 186        CONFIG_AMCC_DEF_ENV                                             \
 187        CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 188        CONFIG_AMCC_DEF_ENV_PPC_OLD                                     \
 189        CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 190        "kernel_addr=FC000000\0"                                        \
 191        "ramdisk_addr=FC180000\0"                                       \
 192        ""
 193
 194#define CONFIG_M88E1111_PHY     1
 195#define CONFIG_IBM_EMAC4_V4     1
 196#define CONFIG_PHY_ADDR         0       /* PHY address, See schematics  */
 197
 198#define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 199#define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 200
 201#define CONFIG_HAS_ETH0
 202#define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 203#define CONFIG_PHY1_ADDR        1
 204
 205/* USB */
 206#ifdef CONFIG_440EPX
 207
 208#undef CONFIG_USB_EHCI  /* OHCI by default */
 209
 210#ifdef CONFIG_USB_EHCI
 211#define CONFIG_USB_EHCI_PPC4XX
 212#define CONFIG_SYS_PPC4XX_USB_ADDR      0xe0000300
 213#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 214#define CONFIG_EHCI_MMIO_BIG_ENDIAN
 215#define CONFIG_EHCI_DESC_BIG_ENDIAN
 216#else /* CONFIG_USB_EHCI */
 217#define CONFIG_USB_OHCI_NEW
 218#define CONFIG_SYS_OHCI_BE_CONTROLLER
 219
 220#undef CONFIG_SYS_USB_OHCI_BOARD_INIT
 221#define CONFIG_SYS_USB_OHCI_CPU_INIT    1
 222#define CONFIG_SYS_USB_OHCI_REGS_BASE   CONFIG_SYS_USB_HOST
 223#define CONFIG_SYS_USB_OHCI_SLOT_NAME   "ppc440"
 224#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
 225#endif
 226
 227#define CONFIG_USB_STORAGE
 228/* Comment this out to enable USB 1.1 device */
 229#define USB_2_0_DEVICE
 230
 231#endif /* CONFIG_440EPX */
 232
 233/* Partitions */
 234#define CONFIG_MAC_PARTITION
 235#define CONFIG_DOS_PARTITION
 236#define CONFIG_ISO_PARTITION
 237
 238/*
 239 * Commands additional to the ones defined in amcc-common.h
 240 */
 241#define CONFIG_CMD_CHIP_CONFIG
 242#define CONFIG_CMD_DTT
 243#define CONFIG_CMD_FAT
 244#define CONFIG_CMD_NAND
 245#define CONFIG_CMD_PCI
 246#define CONFIG_CMD_SDRAM
 247
 248#ifdef CONFIG_440EPX
 249#define CONFIG_CMD_USB
 250#endif
 251
 252#ifndef CONFIG_RAINIER
 253#define CONFIG_SYS_POST_FPU_ON          CONFIG_SYS_POST_FPU
 254#else
 255#define CONFIG_SYS_POST_FPU_ON          0
 256#endif
 257
 258/*
 259 * Don't run the memory POST on the NAND-booting version. It will
 260 * overwrite part of the U-Boot image which is already loaded from NAND
 261 * to SDRAM.
 262 */
 263#if defined(CONFIG_SYS_RAMBOOT)
 264#define CONFIG_SYS_POST_MEMORY_ON       0
 265#else
 266#define CONFIG_SYS_POST_MEMORY_ON       CONFIG_SYS_POST_MEMORY
 267#endif
 268
 269/* POST support */
 270#define CONFIG_POST             (CONFIG_SYS_POST_CACHE     | \
 271                                 CONFIG_SYS_POST_CPU       | \
 272                                 CONFIG_SYS_POST_ETHER     | \
 273                                 CONFIG_SYS_POST_FPU_ON    | \
 274                                 CONFIG_SYS_POST_I2C       | \
 275                                 CONFIG_SYS_POST_MEMORY_ON | \
 276                                 CONFIG_SYS_POST_SPR       | \
 277                                 CONFIG_SYS_POST_UART)
 278
 279#define CONFIG_LOGBUFFER
 280#define CONFIG_SYS_POST_CACHE_ADDR      0x7fff0000      /* free virtual address     */
 281
 282#define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* Otherwise it catches logbuffer as output */
 283
 284#define CONFIG_SUPPORT_VFAT
 285
 286/*
 287 * PCI stuff
 288 */
 289/* General PCI */
 290#define CONFIG_PCI                      /* include pci support          */
 291#define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 292#define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 293#define CONFIG_SYS_PCI_CACHE_LINE_SIZE  0       /* to avoid problems with PNP   */
 294#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 295#define CONFIG_SYS_PCI_TARGBASE 0x80000000      /* PCIaddr mapped to    */
 296                                                /*   CONFIG_SYS_PCI_MEMBASE     */
 297/* Board-specific PCI */
 298#define CONFIG_SYS_PCI_TARGET_INIT
 299#define CONFIG_SYS_PCI_MASTER_INIT
 300#define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
 301
 302#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8   /* AMCC                         */
 303#define CONFIG_SYS_PCI_SUBSYS_ID       0xcafe   /* Whatever                     */
 304
 305/*
 306 * External Bus Controller (EBC) Setup
 307 */
 308
 309/*
 310 * On Sequoia CS0 and CS3 are switched when configuring for NAND booting
 311 */
 312#if !defined(CONFIG_SYS_RAMBOOT)
 313#define CONFIG_SYS_NAND_CS              3       /* NAND chip connected to CSx   */
 314/* Memory Bank 0 (NOR-FLASH) initialization                             */
 315#define CONFIG_SYS_EBC_PB0AP            0x03017200
 316#define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_FLASH_BASE | 0xda000)
 317
 318/* Memory Bank 3 (NAND-FLASH) initialization                            */
 319#define CONFIG_SYS_EBC_PB3AP            0x018003c0
 320#define CONFIG_SYS_EBC_PB3CR            (CONFIG_SYS_NAND_ADDR | 0x1c000)
 321#else
 322#define CONFIG_SYS_NAND_CS              0       /* NAND chip connected to CSx   */
 323/* Memory Bank 3 (NOR-FLASH) initialization                             */
 324#define CONFIG_SYS_EBC_PB3AP            0x03017200
 325#define CONFIG_SYS_EBC_PB3CR            (CONFIG_SYS_FLASH_BASE | 0xda000)
 326
 327/* Memory Bank 0 (NAND-FLASH) initialization                            */
 328#define CONFIG_SYS_EBC_PB0AP            0x018003c0
 329#define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_NAND_ADDR | 0x1c000)
 330#endif
 331
 332/* Memory Bank 2 (CPLD) initialization                                  */
 333#define CONFIG_SYS_EBC_PB2AP            0x24814580
 334#define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_BCSR_BASE | 0x38000)
 335
 336#define CONFIG_SYS_BCSR5_PCI66EN        0x80
 337
 338/*
 339 * NAND FLASH
 340 */
 341#define CONFIG_SYS_MAX_NAND_DEVICE      1
 342#define CONFIG_SYS_NAND_BASE            (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
 343#define CONFIG_SYS_NAND_SELECT_DEVICE  1        /* nand driver supports mutipl. chips */
 344
 345/*
 346 * PPC440 GPIO Configuration
 347 */
 348/* test-only: take GPIO init from pcs440ep ???? in config file */
 349#define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 350{                                                                                       \
 351/* GPIO Core 0 */                                                                       \
 352{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7)     DMA_REQ(2)      */      \
 353{GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6)     DMA_ACK(2)      */      \
 354{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5)     DMA_EOT/TC(2)   */      \
 355{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4)     DMA_REQ(3)      */      \
 356{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3)     DMA_ACK(3)      */      \
 357{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2)     DMA_EOT/TC(3)   */      \
 358{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1)                     */      \
 359{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2)                     */      \
 360{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3)                     */      \
 361{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4)                     */      \
 362{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5)                    */      \
 363{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR                    */      \
 364{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO12                                */      \
 365{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO13                                */      \
 366{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO14                                */      \
 367{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO15                                */      \
 368{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4)                      */      \
 369{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5)                      */      \
 370{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6)                      */      \
 371{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7)                      */      \
 372{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO20 RejectPkt0                     */      \
 373{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO21 RejectPkt1                     */      \
 374{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22                                */      \
 375{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO23 SCPD0                          */      \
 376{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2)                      */      \
 377{GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3)                      */      \
 378{GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26                                */      \
 379{GPIO0_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ    USB2D_RXERROR   */      \
 380{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO28                USB2D_TXVALID   */      \
 381{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO29 EBC_EXT_HDLA   USB2D_PAD_SUSPNDM */    \
 382{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO30 EBC_EXT_ACK    USB2D_XCVRSELECT*/      \
 383{GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/      \
 384},                                                                                      \
 385{                                                                                       \
 386/* GPIO Core 1 */                                                                       \
 387{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0  EBC_DATA(2)     */      \
 388{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1  EBC_DATA(3)     */      \
 389{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_8PIN_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
 390{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 391{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_CTS_N    EBC_DATA(0)     UART3_SIN*/ \
 392{GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N    EBC_DATA(1)     UART3_SOUT*/ \
 393{GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_8PIN_DTR_N UART1_SOUT    */      \
 394{GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_8PIN_RI_N UART1_SIN      */      \
 395{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0)                     */      \
 396{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1)                     */      \
 397{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2)                     */      \
 398{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3)                     */      \
 399{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4)     DMA_ACK(1)      */      \
 400{GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6)     DMA_EOT/TC(1)   */      \
 401{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7)     DMA_REQ(0)      */      \
 402{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8)     DMA_ACK(0)      */      \
 403{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9)     DMA_EOT/TC(0)   */      \
 404{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit  */      \
 405{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit  */      \
 406{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit  */      \
 407{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit  */      \
 408{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit  */      \
 409{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit  */      \
 410{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit  */      \
 411{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit  */      \
 412{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit  */      \
 413{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit  */      \
 414{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit  */      \
 415{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit  */      \
 416{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit  */      \
 417{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit  */      \
 418{GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit  */      \
 419}                                                                                       \
 420}
 421
 422#ifdef CONFIG_VIDEO
 423#define CONFIG_BIOSEMU                  /* x86 bios emulator for vga bios */
 424#define CONFIG_ATI_RADEON_FB            /* use radeon framebuffer driver */
 425#define VIDEO_IO_OFFSET                 0xe8000000
 426#define CONFIG_SYS_ISA_IO_BASE_ADDRESS          VIDEO_IO_OFFSET
 427#define CONFIG_VIDEO_SW_CURSOR
 428#define CONFIG_VIDEO_LOGO
 429#define CONFIG_CFB_CONSOLE
 430#define CONFIG_SPLASH_SCREEN
 431#define CONFIG_VGA_AS_SINGLE_DEVICE
 432#define CONFIG_CMD_BMP
 433#endif
 434
 435#endif /* __CONFIG_H */
 436