1/* 2 * Copyright 2014, Freescale Semiconductor 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7#ifndef _ASM_ARMV8_FSL_LSCH3_CONFIG_ 8#define _ASM_ARMV8_FSL_LSCH3_CONFIG_ 9 10#include <fsl_ddrc_version.h> 11#define CONFIG_MP 12#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ 13/* Link Definitions */ 14#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0) 15 16#define CONFIG_SYS_IMMR 0x01000000 17#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) 18#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000) 19#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000 20#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000) 21#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000) 22#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000) 23#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000) 24#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000) 25#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000) 26#define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) 27#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) 28#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) 29#define CONFIG_SYS_FSL_TIMER_ADDR 0x023d0000 30#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \ 31 0x18A0) 32 33#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL 34#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL 35#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL 36#define CONFIG_SYS_FSL_DCSR_DDR4_ADDR 0x700133000ULL 37 38#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000) 39#define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000) 40#define I2C3_BASE_ADDR (CONFIG_SYS_IMMR + 0x01020000) 41#define I2C4_BASE_ADDR (CONFIG_SYS_IMMR + 0x01030000) 42 43/* TZ Protection Controller Definitions */ 44#define TZPC_BASE 0x02200000 45#define TZPCR0SIZE_BASE (TZPC_BASE) 46#define TZPCDECPROT_0_STAT_BASE (TZPC_BASE + 0x800) 47#define TZPCDECPROT_0_SET_BASE (TZPC_BASE + 0x804) 48#define TZPCDECPROT_0_CLR_BASE (TZPC_BASE + 0x808) 49#define TZPCDECPROT_1_STAT_BASE (TZPC_BASE + 0x80C) 50#define TZPCDECPROT_1_SET_BASE (TZPC_BASE + 0x810) 51#define TZPCDECPROT_1_CLR_BASE (TZPC_BASE + 0x814) 52#define TZPCDECPROT_2_STAT_BASE (TZPC_BASE + 0x818) 53#define TZPCDECPROT_2_SET_BASE (TZPC_BASE + 0x81C) 54#define TZPCDECPROT_2_CLR_BASE (TZPC_BASE + 0x820) 55 56/* TZ Address Space Controller Definitions */ 57#define TZASC1_BASE 0x01100000 /* as per CCSR map. */ 58#define TZASC2_BASE 0x01110000 /* as per CCSR map. */ 59#define TZASC3_BASE 0x01120000 /* as per CCSR map. */ 60#define TZASC4_BASE 0x01130000 /* as per CCSR map. */ 61#define TZASC_BUILD_CONFIG_REG(x) ((TZASC1_BASE + (x * 0x10000))) 62#define TZASC_ACTION_REG(x) ((TZASC1_BASE + (x * 0x10000)) + 0x004) 63#define TZASC_GATE_KEEPER(x) ((TZASC1_BASE + (x * 0x10000)) + 0x008) 64#define TZASC_REGION_BASE_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x100) 65#define TZASC_REGION_BASE_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x104) 66#define TZASC_REGION_TOP_LOW_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x108) 67#define TZASC_REGION_TOP_HIGH_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x10C) 68#define TZASC_REGION_ATTRIBUTES_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x110) 69#define TZASC_REGION_ID_ACCESS_0(x) ((TZASC1_BASE + (x * 0x10000)) + 0x114) 70 71/* Generic Interrupt Controller Definitions */ 72#define GICD_BASE 0x06000000 73#define GICR_BASE 0x06100000 74 75/* SMMU Defintions */ 76#define SMMU_BASE 0x05000000 /* GR0 Base */ 77 78/* DDR */ 79#define CONFIG_SYS_FSL_DDR_LE 80#define CONFIG_VERY_BIG_RAM 81#ifdef CONFIG_SYS_FSL_DDR4 82#define CONFIG_SYS_FSL_DDRC_GEN4 83#else 84#define CONFIG_SYS_FSL_DDRC_ARM_GEN3 /* Enable Freescale ARM DDR3 driver */ 85#endif 86#define CONFIG_SYS_FSL_DDR /* Freescale DDR driver */ 87#define CONFIG_SYS_LS2_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) 88#define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_LS2_DDR_BLOCK1_SIZE 89#define CONFIG_SYS_FSL_DDR_VER FSL_DDR_VER_5_0 90 91 92/* IFC */ 93#define CONFIG_SYS_FSL_IFC_LE 94 95#ifdef CONFIG_LS2085A 96#define CONFIG_MAX_CPUS 16 97#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 98#define CONFIG_NUM_DDR_CONTROLLERS 3 99#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } 100#else 101#error SoC not defined 102#endif 103 104#ifdef CONFIG_LS2085A 105#define CONFIG_SYS_FSL_ERRATUM_A008336 106#define CONFIG_SYS_FSL_ERRATUM_A008514 107#endif 108 109#endif /* _ASM_ARMV8_FSL_LSCH3_CONFIG_ */ 110