1/* 2 * UniPhier DDR PHY registers 3 * 4 * Copyright (C) 2014 Panasonic Corporation 5 * Author: Masahiro Yamada <yamada.m@jp.panasonic.com> 6 * 7 * SPDX-License-Identifier: GPL-2.0+ 8 */ 9 10#ifndef ARCH_DDRPHY_REGS_H 11#define ARCH_DDRPHY_REGS_H 12 13#include <linux/compiler.h> 14 15#ifndef __ASSEMBLY__ 16 17struct ddrphy { 18 u32 ridr; /* Revision Identification Register */ 19 u32 pir; /* PHY Initialixation Register */ 20 u32 pgcr[2]; /* PHY General Configuration Register */ 21 u32 pgsr[2]; /* PHY General Status Register */ 22 u32 pllcr; /* PLL Control Register */ 23 u32 ptr[5]; /* PHY Timing Register */ 24 u32 acmdlr; /* AC Master Delay Line Register */ 25 u32 acbdlr; /* AC Bit Delay Line Register */ 26 u32 aciocr; /* AC I/O Configuration Register */ 27 u32 dxccr; /* DATX8 Common Configuration Register */ 28 u32 dsgcr; /* DDR System General Configuration Register */ 29 u32 dcr; /* DRAM Configuration Register */ 30 u32 dtpr[3]; /* DRAM Timing Parameters Register */ 31 u32 mr0; /* Mode Register 0 */ 32 u32 mr1; /* Mode Register 1 */ 33 u32 mr2; /* Mode Register 2 */ 34 u32 mr3; /* Mode Register 3 */ 35 u32 odtcr; /* ODT Configuration Register */ 36 u32 dtcr; /* Data Training Configuration Register */ 37 u32 dtar[4]; /* Data Training Address Register */ 38 u32 dtdr[2]; /* Data Training Data Register */ 39 u32 dtedr[2]; /* Data Training Eye Data Register */ 40 u32 rsv0[13]; /* Reserved */ 41 u32 dcuar; /* DCU Address Register */ 42 u32 dcudr; /* DCU Data Register */ 43 u32 dcurr; /* DCU Run Register */ 44 u32 dculr; /* DCU Loop Register */ 45 u32 dcugcr; /* DCU General Configuration Register */ 46 u32 dcutpr; /* DCU Timing Parameters Register */ 47 u32 dcusr[2]; /* DCU Status Register */ 48 u32 rsv1[8]; /* Reserved */ 49 u32 bistrr; /* BIST Run Register */ 50 u32 bistwcr; /* BIST Word Count Register */ 51 u32 bistmskr[3]; /* BIST Mask Register */ 52 u32 bistlsr; /* BIST LFSR Sed Register */ 53 u32 bistar[3]; /* BIST Address Register */ 54 u32 bistudpr; /* BIST User Data Pattern Register */ 55 u32 bistgsr; /* BIST General Status Register */ 56 u32 bistwer; /* BIST Word Error Register */ 57 u32 bistber[4]; /* BIST Bit Error Register */ 58 u32 bistwcsr; /* BIST Word Count Status Register */ 59 u32 bistfwr[3]; /* BIST Fail Word Register */ 60 u32 rsv2[10]; /* Reserved */ 61 u32 gpr[2]; /* General Purpose Register */ 62 struct ddrphy_zq { /* ZQ */ 63 u32 cr[2]; /* Impedance Control Register */ 64 u32 sr[2]; /* Impedance Status Register */ 65 } zq[4]; 66 struct ddrphy_datx8 { /* DATX8 */ 67 u32 gcr; /* General Configuration Register */ 68 u32 gsr[2]; /* General Status Register */ 69 u32 bdlr[5]; /* Bit Delay Line Register */ 70 u32 lcdlr[3]; /* Local Calibrated Delay Line Register */ 71 u32 mdlr; /* Master Delay Line Register */ 72 u32 gtr; /* General Timing Register */ 73 u32 rsv[3]; /* Reserved */ 74 } dx[9]; 75}; 76 77#endif /* __ASSEMBLY__ */ 78 79#define PIR_INIT (1 << 0) /* Initialization Trigger */ 80#define PIR_ZCAL (1 << 1) /* Impedance Calibration */ 81#define PIR_PLLINIT (1 << 4) /* PLL Initialization */ 82#define PIR_DCAL (1 << 5) /* DDL Calibration */ 83#define PIR_PHYRST (1 << 6) /* PHY Reset */ 84#define PIR_DRAMRST (1 << 7) /* DRAM Reset */ 85#define PIR_DRAMINIT (1 << 8) /* DRAM Initialization */ 86#define PIR_WL (1 << 9) /* Write Leveling */ 87#define PIR_QSGATE (1 << 10) /* Read DQS Gate Training */ 88#define PIR_WLADJ (1 << 11) /* Write Leveling Adjust */ 89#define PIR_RDDSKW (1 << 12) /* Read Data Bit Deskew */ 90#define PIR_WRDSKW (1 << 13) /* Write Data Bit Deskew */ 91#define PIR_RDEYE (1 << 14) /* Read Data Eye Training */ 92#define PIR_WREYE (1 << 15) /* Write Data Eye Training */ 93#define PIR_LOCKBYP (1 << 28) /* PLL Lock Bypass */ 94#define PIR_DCALBYP (1 << 29) /* DDL Calibration Bypass */ 95#define PIR_ZCALBYP (1 << 30) /* Impedance Calib Bypass */ 96#define PIR_INITBYP (1 << 31) /* Initialization Bypass */ 97 98#define PGSR0_IDONE (1 << 0) /* Initialization Done */ 99#define PGSR0_PLDONE (1 << 1) /* PLL Lock Done */ 100#define PGSR0_DCDONE (1 << 2) /* DDL Calibration Done */ 101#define PGSR0_ZCDONE (1 << 3) /* Impedance Calibration Done */ 102#define PGSR0_DIDONE (1 << 4) /* DRAM Initialization Done */ 103#define PGSR0_WLDONE (1 << 5) /* Write Leveling Done */ 104#define PGSR0_QSGDONE (1 << 6) /* DQS Gate Training Done */ 105#define PGSR0_WLADONE (1 << 7) /* Write Leveling Adjust Done */ 106#define PGSR0_RDDONE (1 << 8) /* Read Bit Deskew Done */ 107#define PGSR0_WDDONE (1 << 9) /* Write Bit Deskew Done */ 108#define PGSR0_REDONE (1 << 10) /* Read Eye Training Done */ 109#define PGSR0_WEDONE (1 << 11) /* Write Eye Training Done */ 110#define PGSR0_IERR (1 << 16) /* Initialization Error */ 111#define PGSR0_PLERR (1 << 17) /* PLL Lock Error */ 112#define PGSR0_DCERR (1 << 18) /* DDL Calibration Error */ 113#define PGSR0_ZCERR (1 << 19) /* Impedance Calib Error */ 114#define PGSR0_DIERR (1 << 20) /* DRAM Initialization Error */ 115#define PGSR0_WLERR (1 << 21) /* Write Leveling Error */ 116#define PGSR0_QSGERR (1 << 22) /* DQS Gate Training Error */ 117#define PGSR0_WLAERR (1 << 23) /* Write Leveling Adj Error */ 118#define PGSR0_RDERR (1 << 24) /* Read Bit Deskew Error */ 119#define PGSR0_WDERR (1 << 25) /* Write Bit Deskew Error */ 120#define PGSR0_REERR (1 << 26) /* Read Eye Training Error */ 121#define PGSR0_WEERR (1 << 27) /* Write Eye Training Error */ 122#define PGSR0_DTERR_SHIFT 28 /* Data Training Error Status*/ 123#define PGSR0_DTERR (7 << (PGSR0_DTERR_SHIFT)) 124#define PGSR0_APLOCK (1 << 31) /* AC PLL Lock */ 125 126#define DXCCR_DQSRES_OPEN (0 << 5) 127#define DXCCR_DQSRES_688_OHM (1 << 5) 128#define DXCCR_DQSRES_611_OHM (2 << 5) 129#define DXCCR_DQSRES_550_OHM (3 << 5) 130#define DXCCR_DQSRES_500_OHM (4 << 5) 131#define DXCCR_DQSRES_458_OHM (5 << 5) 132#define DXCCR_DQSRES_393_OHM (6 << 5) 133#define DXCCR_DQSRES_344_OHM (7 << 5) 134 135#define DXCCR_DQSNRES_OPEN (0 << 9) 136#define DXCCR_DQSNRES_688_OHM (1 << 9) 137#define DXCCR_DQSNRES_611_OHM (2 << 9) 138#define DXCCR_DQSNRES_550_OHM (3 << 9) 139#define DXCCR_DQSNRES_500_OHM (4 << 9) 140#define DXCCR_DQSNRES_458_OHM (5 << 9) 141#define DXCCR_DQSNRES_393_OHM (6 << 9) 142#define DXCCR_DQSNRES_344_OHM (7 << 9) 143 144#define DTCR_DTRANK_SHIFT 4 /* Data Training Rank */ 145#define DTCR_DTRANK_MASK (0x3 << (DTCR_DTRANK_SHIFT)) 146#define DTCR_DTMPR (1 << 6) /* Data Training using MPR */ 147#define DTCR_RNKEN_SHIFT 24 /* Rank Enable */ 148#define DTCR_RNKEN_MASK (0xf << (DTCR_RNKEN_SHIFT)) 149 150#define DXGCR_WLRKEN_SHIFT 26 /* Write Level Rank Enable */ 151#define DXGCR_WLRKEN_MASK (0xf << (DXGCR_WLRKEN_SHIFT)) 152 153/* SoC-specific parameters */ 154#define NR_DATX8_PER_DDRPHY 2 155 156#if defined(CONFIG_MACH_PH1_LD4) || defined(CONFIG_MACH_PH1_SLD8) 157#define NR_DDRPHY_PER_CH 1 158#else 159#define NR_DDRPHY_PER_CH 2 160#endif 161 162#define NR_DDRCH 2 163 164#define DDRPHY_BASE(ch, phy) (0x5bc01000 + 0x200000 * (ch) + 0x1000 * (phy)) 165 166#ifndef __ASSEMBLY__ 167void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size); 168void ddrphy_prepare_training(struct ddrphy __iomem *phy, int rank); 169int ddrphy_training(struct ddrphy __iomem *phy); 170#endif 171 172#endif /* ARCH_DDRPHY_REGS_H */ 173