LXR uboot/board/atmel/atstk1000/atstk1000.c

   1/*
   2 * Copyright (C) 2005-2006 Atmel Corporation
   3 *
   4 * SPDX-License-Identifier:     GPL-2.0+
   5 */
   6#include <common.h>
   7
   8#include <asm/io.h>
   9#include <asm/sdram.h>
  10#include <asm/arch/clk.h>
  11#include <asm/arch/hmatrix.h>
  12#include <asm/arch/mmu.h>
  13#include <asm/arch/portmux.h>
  14#include <netdev.h>
  15
  16DECLARE_GLOBAL_DATA_PTR;
  17
  18struct mmu_vm_range mmu_vmr_table[CONFIG_SYS_NR_VM_REGIONS] = {
  19        {
  20                .virt_pgno      = CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT,
  21                .nr_pages       = CONFIG_SYS_FLASH_SIZE >> MMU_PAGE_SHIFT,
  22                .phys           = (CONFIG_SYS_FLASH_BASE >> MMU_PAGE_SHIFT)
  23                                        | MMU_VMR_CACHE_NONE,
  24        }, {
  25                .virt_pgno      = CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT,
  26                .nr_pages       = EBI_SDRAM_SIZE >> MMU_PAGE_SHIFT,
  27                .phys           = (CONFIG_SYS_SDRAM_BASE >> MMU_PAGE_SHIFT)
  28                                        | MMU_VMR_CACHE_WRBACK,
  29        },
  30};
  31
  32static const struct sdram_config sdram_config = {
  33#if defined(CONFIG_ATSTK1006)
  34        /* Dual MT48LC16M16A2-7E (64 MB) on daughterboard */
  35        .data_bits      = SDRAM_DATA_32BIT,
  36        .row_bits       = 13,
  37        .col_bits       = 9,
  38        .bank_bits      = 2,
  39        .cas            = 2,
  40        .twr            = 2,
  41        .trc            = 7,
  42        .trp            = 2,
  43        .trcd           = 2,
  44        .tras           = 4,
  45        .txsr           = 7,
  46        /* 7.81 us */
  47        .refresh_period = (781 * (SDRAMC_BUS_HZ / 1000)) / 100000,
  48#else
  49        /* MT48LC2M32B2P-5 (8 MB) on motherboard */
  50#ifdef CONFIG_ATSTK1004
  51        .data_bits      = SDRAM_DATA_16BIT,
  52#else
  53        .data_bits      = SDRAM_DATA_32BIT,
  54#endif
  55#ifdef CONFIG_ATSTK1000_16MB_SDRAM
  56        /* MT48LC4M32B2P-6 (16 MB) on mod'ed motherboard */
  57        .row_bits       = 12,
  58#else
  59        .row_bits       = 11,
  60#endif
  61        .col_bits       = 8,
  62        .bank_bits      = 2,
  63        .cas            = 3,
  64        .twr            = 2,
  65        .trc            = 7,
  66        .trp            = 2,
  67        .trcd           = 2,
  68        .tras           = 5,
  69        .txsr           = 5,
  70        /* 15.6 us */
  71        .refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000,
  72#endif
  73};
  74
  75int board_early_init_f(void)
  76{
  77        /* Enable SDRAM in the EBI mux */
  78        hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE));
  79
  80        portmux_enable_ebi(sdram_config.data_bits, 23, 0, PORTMUX_DRIVE_HIGH);
  81        sdram_init(uncached(EBI_SDRAM_BASE), &sdram_config);
  82
  83        portmux_enable_usart1(PORTMUX_DRIVE_MIN);
  84
  85#if defined(CONFIG_MACB)
  86        portmux_enable_macb0(PORTMUX_MACB_MII, PORTMUX_DRIVE_LOW);
  87        portmux_enable_macb1(PORTMUX_MACB_MII, PORTMUX_DRIVE_LOW);
  88#endif
  89#if defined(CONFIG_MMC)
  90        portmux_enable_mmci(0, PORTMUX_MMCI_4BIT, PORTMUX_DRIVE_LOW);
  91#endif
  92
  93        return 0;
  94}
  95
  96int board_early_init_r(void)
  97{
  98        gd->bd->bi_phy_id[0] = 0x10;
  99        gd->bd->bi_phy_id[1] = 0x11;
 100        return 0;
 101}
 102
 103#ifdef CONFIG_CMD_NET
 104int board_eth_init(bd_t *bi)
 105{
 106        macb_eth_initialize(0, (void *)ATMEL_BASE_MACB0, bi->bi_phy_id[0]);
 107        macb_eth_initialize(1, (void *)ATMEL_BASE_MACB1, bi->bi_phy_id[1]);
 108        return 0;
 109}
 110#endif
 111