LXR uboot/board/calao/sbc35_a9g20/sbc35

   1/*
   2 * (C) Copyright 2007-2008
   3 * Stelian Pop <stelian@popies.net>
   4 * Lead Tech Design <www.leadtechdesign.com>
   5 *
   6 * Copyright (C) 2009
   7 * Albin Tonnerre, Free-Electrons <albin.tonnerre@free-electrons.com>
   8 *
   9 * SPDX-License-Identifier:     GPL-2.0+
  10 */
  11
  12#include <common.h>
  13#include <asm/io.h>
  14#include <asm/arch/at91sam9260_matrix.h>
  15#include <asm/arch/at91sam9_smc.h>
  16#include <asm/arch/at91_common.h>
  17#include <asm/arch/at91_pmc.h>
  18#include <asm/arch/gpio.h>
  19
  20#if defined(CONFIG_RESET_PHY_R) && defined(CONFIG_MACB)
  21#include <net.h>
  22#endif
  23#include <netdev.h>
  24
  25DECLARE_GLOBAL_DATA_PTR;
  26
  27/* ------------------------------------------------------------------------- */
  28/*
  29 * Miscelaneous platform dependent initialisations
  30 */
  31
  32#ifdef CONFIG_CMD_NAND
  33static void sbc35_a9g20_nand_hw_init(void)
  34{
  35        struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  36        struct at91_smc *smc = (struct at91_smc *)ATMEL_BASE_SMC;
  37        struct at91_matrix *matrix = (struct at91_matrix *)ATMEL_BASE_MATRIX;
  38        unsigned long csa;
  39
  40        /* Enable CS3 */
  41        csa = readl(&matrix->ebicsa);
  42        csa |= AT91_MATRIX_CS3A_SMC_SMARTMEDIA;
  43        writel(csa, &matrix->ebicsa);
  44
  45        /* Configure SMC CS3 for NAND/SmartMedia */
  46        writel(AT91_SMC_SETUP_NWE(1) | AT91_SMC_SETUP_NCS_WR(0) |
  47                AT91_SMC_SETUP_NRD(1) | AT91_SMC_SETUP_NCS_RD(0),
  48                &smc->cs[3].setup);
  49        writel(AT91_SMC_PULSE_NWE(3) | AT91_SMC_PULSE_NCS_WR(3) |
  50                AT91_SMC_PULSE_NRD(3) | AT91_SMC_PULSE_NCS_RD(3),
  51                &smc->cs[3].pulse);
  52        writel(AT91_SMC_CYCLE_NWE(5) | AT91_SMC_CYCLE_NRD(5),
  53                &smc->cs[3].cycle);
  54        writel(AT91_SMC_MODE_RM_NRD | AT91_SMC_MODE_WM_NWE |
  55                AT91_SMC_MODE_EXNW_DISABLE |
  56#ifdef CONFIG_SYS_NAND_DBW_16
  57                AT91_SMC_MODE_DBW_16 |
  58#else /* CONFIG_SYS_NAND_DBW_8 */
  59                AT91_SMC_MODE_DBW_8 |
  60#endif
  61                AT91_SMC_MODE_TDF_CYCLE(2),
  62                &smc->cs[3].mode);
  63
  64        writel(1 << ATMEL_ID_PIOC, &pmc->pcer);
  65
  66        /* Configure RDY/BSY */
  67        at91_set_gpio_input(CONFIG_SYS_NAND_READY_PIN, 1);
  68
  69        /* Enable NandFlash */
  70        at91_set_gpio_output(CONFIG_SYS_NAND_ENABLE_PIN, 1);
  71}
  72#endif
  73
  74#ifdef CONFIG_MACB
  75static void sbc35_a9g20_macb_hw_init(void)
  76{
  77        struct at91_pmc *pmc = (struct at91_pmc *)ATMEL_BASE_PMC;
  78        struct at91_port *pioa = (struct at91_port *)ATMEL_BASE_PIOA;
  79
  80        /* Enable EMAC clock */
  81        writel(1 << ATMEL_ID_EMAC0, &pmc->pcer);
  82
  83        /*
  84         * Disable pull-up on:
  85         *      RXDV (PA17) => PHY normal mode (not Test mode)
  86         *      ERX0 (PA14) => PHY ADDR0
  87         *      ERX1 (PA15) => PHY ADDR1
  88         *      ERX2 (PA25) => PHY ADDR2
  89         *      ERX3 (PA26) => PHY ADDR3
  90         *      ECRS (PA28) => PHY ADDR4  => PHYADDR = 0x0
  91         *
  92         * PHY has internal pull-down
  93         */
  94        writel(pin_to_mask(AT91_PIN_PA14) |
  95               pin_to_mask(AT91_PIN_PA15) |
  96               pin_to_mask(AT91_PIN_PA17) |
  97               pin_to_mask(AT91_PIN_PA25) |
  98               pin_to_mask(AT91_PIN_PA26) |
  99               pin_to_mask(AT91_PIN_PA28),
 100               &pioa->pudr);
 101
 102        at91_phy_reset();
 103
 104        /* Re-enable pull-up */
 105        writel(pin_to_mask(AT91_PIN_PA14) |
 106               pin_to_mask(AT91_PIN_PA15) |
 107               pin_to_mask(AT91_PIN_PA17) |
 108               pin_to_mask(AT91_PIN_PA25) |
 109               pin_to_mask(AT91_PIN_PA26) |
 110               pin_to_mask(AT91_PIN_PA28),
 111               &pioa->puer);
 112
 113        at91_macb_hw_init();
 114}
 115#endif
 116
 117int board_init(void)
 118{
 119        /* adress of boot parameters */
 120        gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
 121
 122        at91_seriald_hw_init();
 123        sbc35_a9g20_nand_hw_init();
 124#ifdef CONFIG_ATMEL_SPI
 125        at91_spi0_hw_init(1 << 4 | 1 << 5);
 126#endif
 127#ifdef CONFIG_MACB
 128        sbc35_a9g20_macb_hw_init();
 129#endif
 130
 131        return 0;
 132}
 133
 134int dram_init(void)
 135{
 136        gd->ram_size = get_ram_size(
 137                (void *)CONFIG_SYS_SDRAM_BASE,
 138                CONFIG_SYS_SDRAM_SIZE);
 139        return 0;
 140}
 141
 142#ifdef CONFIG_RESET_PHY_R
 143void reset_phy(void)
 144{
 145}
 146#endif
 147
 148int board_eth_init(bd_t *bis)
 149{
 150        int rc = 0;
 151#ifdef CONFIG_MACB
 152        rc = macb_eth_initialize(0, (void *)ATMEL_BASE_EMAC0, 0x00);
 153#endif
 154        return rc;
 155}
 156