uboot/board/denx/m53evk/imximage.cfg
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   1/*
   2 * DENX M53 DRAM init values
   3 * Copyright (C) 2012-2013 Marek Vasut <marex@denx.de>
   4 *
   5 * SPDX-License-Identifier:     GPL-2.0+
   6 *
   7 * Refer docs/README.imxmage for more details about how-to configure
   8 * and create imximage boot image
   9 *
  10 * The syntax is taken as close as possible with the kwbimage
  11 */
  12#include <asm/imx-common/imximage.cfg>
  13
  14/* image version */
  15IMAGE_VERSION   2
  16
  17
  18/* Boot Offset 0x400, valid for both SD and NAND boot. */
  19BOOT_OFFSET     FLASH_OFFSET_STANDARD
  20
  21/*
  22 * Device Configuration Data (DCD)
  23 *
  24 * Each entry must have the format:
  25 * Addr-type           Address        Value
  26 *
  27 * where:
  28 *      Addr-type register length (1,2 or 4 bytes)
  29 *      Address   absolute address of the register
  30 *      value     value to be stored in the register
  31 */
  32DATA 4 0x53fa86f4 0x00000000     /* GRP_DDRMODE_CTL */
  33DATA 4 0x53fa8714 0x00000000     /* GRP_DDRMODE */
  34DATA 4 0x53fa86fc 0x00000000     /* GRP_DDRPKE */
  35DATA 4 0x53fa8724 0x04000000     /* GRP_DDR_TYPE */
  36
  37DATA 4 0x53fa872c 0x00300000     /* GRP_B3DS */
  38DATA 4 0x53fa8554 0x00300000     /* DRAM_DQM3 */
  39DATA 4 0x53fa8558 0x00300040     /* DRAM_SDQS3 */
  40
  41DATA 4 0x53fa8728 0x00300000     /* GRP_B2DS */
  42DATA 4 0x53fa8560 0x00300000     /* DRAM_DQM2 */
  43DATA 4 0x53fa8568 0x00300040     /* DRAM_SDQS2 */
  44
  45DATA 4 0x53fa871c 0x00300000     /* GRP_B1DS */
  46DATA 4 0x53fa8594 0x00300000     /* DRAM_DQM1 */
  47DATA 4 0x53fa8590 0x00300040     /* DRAM_SDQS1 */
  48
  49DATA 4 0x53fa8718 0x00300000     /* GRP_B0DS */
  50DATA 4 0x53fa8584 0x00300000     /* DRAM_DQM0 */
  51DATA 4 0x53fa857c 0x00300040     /* DRAM_SDQS0 */
  52
  53DATA 4 0x53fa8578 0x00300000     /* DRAM_SDCLK_0 */
  54DATA 4 0x53fa8570 0x00300000     /* DRAM_SDCLK_1 */
  55
  56DATA 4 0x53fa8574 0x00300000     /* DRAM_CAS */
  57DATA 4 0x53fa8588 0x00300000     /* DRAM_RAS */
  58DATA 4 0x53fa86f0 0x00300000     /* GRP_ADDDS */
  59DATA 4 0x53fa8720 0x00300000     /* GRP_CTLDS */
  60
  61DATA 4 0x53fa8564 0x00300040     /* DRAM_SDODT1 */
  62DATA 4 0x53fa8580 0x00300040     /* DRAM_SDODT0 */
  63
  64/* ESDCTL */
  65DATA 4 0x63fd9088 0x32383535
  66DATA 4 0x63fd9090 0x40383538
  67DATA 4 0x63fd907c 0x0136014d
  68DATA 4 0x63fd9080 0x01510141
  69
  70DATA 4 0x63fd9018 0x00011740
  71DATA 4 0x63fd9000 0xc3190000
  72DATA 4 0x63fd900c 0x555952e3
  73DATA 4 0x63fd9010 0xb68e8b63
  74DATA 4 0x63fd9014 0x01ff00db
  75DATA 4 0x63fd902c 0x000026d2
  76DATA 4 0x63fd9030 0x009f0e21
  77DATA 4 0x63fd9008 0x12273030
  78DATA 4 0x63fd9004 0x0002002d
  79DATA 4 0x63fd901c 0x00008032
  80DATA 4 0x63fd901c 0x00008033
  81DATA 4 0x63fd901c 0x00028031
  82DATA 4 0x63fd901c 0x092080b0
  83DATA 4 0x63fd901c 0x04008040
  84DATA 4 0x63fd901c 0x0000803a
  85DATA 4 0x63fd901c 0x0000803b
  86DATA 4 0x63fd901c 0x00028039
  87DATA 4 0x63fd901c 0x09208138
  88DATA 4 0x63fd901c 0x04008048
  89DATA 4 0x63fd9020 0x00001800
  90DATA 4 0x63fd9040 0x04b80003
  91DATA 4 0x63fd9058 0x00022227
  92DATA 4 0x63fd901c 0x00000000
  93