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9#include <asm/arch/clock.h>
10#include <asm/arch/iomux.h>
11#include <asm/arch/imx-regs.h>
12#include <asm/arch/mx6-pins.h>
13#include <asm/arch/sys_proto.h>
14#include <asm/gpio.h>
15#include <asm/imx-common/iomux-v3.h>
16#include <asm/imx-common/mxc_i2c.h>
17#include <asm/imx-common/spi.h>
18#include <asm/io.h>
19#include <linux/sizes.h>
20#include <common.h>
21#include <fsl_esdhc.h>
22#include <i2c.h>
23#include <mmc.h>
24#include <netdev.h>
25#include <power/pmic.h>
26#include <power/pfuze100_pmic.h>
27#include "../common/pfuze.h"
28#include <usb.h>
29#include <usb/ehci-fsl.h>
30
31DECLARE_GLOBAL_DATA_PTR;
32
33#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
34 PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
35 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
36
37#define USDHC_PAD_CTRL (PAD_CTL_PUS_22K_UP | \
38 PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \
39 PAD_CTL_SRE_FAST | PAD_CTL_HYS)
40
41#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
42 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
43 PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
44
45#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \
46 PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
47
48#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
49 PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
50 PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \
51 PAD_CTL_ODE | PAD_CTL_SRE_FAST)
52
53#define OTGID_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
54 PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\
55 PAD_CTL_DSE_80ohm | PAD_CTL_HYS | \
56 PAD_CTL_SRE_FAST)
57
58#define ETH_PHY_RESET IMX_GPIO_NR(4, 21)
59
60int dram_init(void)
61{
62 gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE);
63
64 return 0;
65}
66
67static iomux_v3_cfg_t const uart1_pads[] = {
68 MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
69 MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
70};
71
72static iomux_v3_cfg_t const usdhc1_pads[] = {
73
74 MX6_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
75 MX6_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
76 MX6_PAD_SD1_DAT0__USDHC1_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
77 MX6_PAD_SD1_DAT1__USDHC1_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
78 MX6_PAD_SD1_DAT2__USDHC1_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
79 MX6_PAD_SD1_DAT3__USDHC1_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
80 MX6_PAD_SD1_DAT4__USDHC1_DAT4 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
81 MX6_PAD_SD1_DAT5__USDHC1_DAT5 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
82 MX6_PAD_SD1_DAT6__USDHC1_DAT6 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
83 MX6_PAD_SD1_DAT7__USDHC1_DAT7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
84
85
86 MX6_PAD_KEY_ROW7__GPIO_4_7 | MUX_PAD_CTRL(NO_PAD_CTRL),
87};
88
89static iomux_v3_cfg_t const usdhc2_pads[] = {
90 MX6_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
91 MX6_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
92 MX6_PAD_SD2_DAT0__USDHC2_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
93 MX6_PAD_SD2_DAT1__USDHC2_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
94 MX6_PAD_SD2_DAT2__USDHC2_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
95 MX6_PAD_SD2_DAT3__USDHC2_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
96
97
98 MX6_PAD_SD2_DAT7__GPIO_5_0 | MUX_PAD_CTRL(NO_PAD_CTRL),
99};
100
101static iomux_v3_cfg_t const usdhc3_pads[] = {
102 MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL),
103 MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL),
104 MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
105 MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
106 MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
107 MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
108
109
110 MX6_PAD_REF_CLK_32K__GPIO_3_22 | MUX_PAD_CTRL(NO_PAD_CTRL),
111};
112
113static iomux_v3_cfg_t const fec_pads[] = {
114 MX6_PAD_FEC_MDC__FEC_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL),
115 MX6_PAD_FEC_MDIO__FEC_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL),
116 MX6_PAD_FEC_CRS_DV__FEC_RX_DV | MUX_PAD_CTRL(ENET_PAD_CTRL),
117 MX6_PAD_FEC_RXD0__FEC_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
118 MX6_PAD_FEC_RXD1__FEC_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
119 MX6_PAD_FEC_TX_EN__FEC_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL),
120 MX6_PAD_FEC_TXD0__FEC_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL),
121 MX6_PAD_FEC_TXD1__FEC_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL),
122 MX6_PAD_FEC_REF_CLK__FEC_REF_OUT | MUX_PAD_CTRL(ENET_PAD_CTRL),
123 MX6_PAD_FEC_RX_ER__GPIO_4_19 | MUX_PAD_CTRL(NO_PAD_CTRL),
124 MX6_PAD_FEC_TX_CLK__GPIO_4_21 | MUX_PAD_CTRL(NO_PAD_CTRL),
125};
126
127#ifdef CONFIG_MXC_SPI
128static iomux_v3_cfg_t ecspi1_pads[] = {
129 MX6_PAD_ECSPI1_MISO__ECSPI_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
130 MX6_PAD_ECSPI1_MOSI__ECSPI_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
131 MX6_PAD_ECSPI1_SCLK__ECSPI_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
132 MX6_PAD_ECSPI1_SS0__GPIO4_IO11 | MUX_PAD_CTRL(NO_PAD_CTRL),
133};
134
135int board_spi_cs_gpio(unsigned bus, unsigned cs)
136{
137 return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(4, 11)) : -1;
138}
139
140static void setup_spi(void)
141{
142 imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
143}
144#endif
145
146static void setup_iomux_uart(void)
147{
148 imx_iomux_v3_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
149}
150
151static void setup_iomux_fec(void)
152{
153 imx_iomux_v3_setup_multiple_pads(fec_pads, ARRAY_SIZE(fec_pads));
154
155
156 gpio_direction_output(ETH_PHY_RESET , 0);
157 udelay(1000);
158 gpio_set_value(ETH_PHY_RESET, 1);
159}
160
161#define USDHC1_CD_GPIO IMX_GPIO_NR(4, 7)
162#define USDHC2_CD_GPIO IMX_GPIO_NR(5, 0)
163#define USDHC3_CD_GPIO IMX_GPIO_NR(3, 22)
164
165static struct fsl_esdhc_cfg usdhc_cfg[3] = {
166 {USDHC1_BASE_ADDR},
167 {USDHC2_BASE_ADDR, 0, 4},
168 {USDHC3_BASE_ADDR, 0, 4},
169};
170
171int board_mmc_getcd(struct mmc *mmc)
172{
173 struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
174 int ret = 0;
175
176 switch (cfg->esdhc_base) {
177 case USDHC1_BASE_ADDR:
178 ret = !gpio_get_value(USDHC1_CD_GPIO);
179 break;
180 case USDHC2_BASE_ADDR:
181 ret = !gpio_get_value(USDHC2_CD_GPIO);
182 break;
183 case USDHC3_BASE_ADDR:
184 ret = !gpio_get_value(USDHC3_CD_GPIO);
185 break;
186 }
187
188 return ret;
189}
190
191int board_mmc_init(bd_t *bis)
192{
193 int i, ret;
194
195
196
197
198
199
200
201
202 for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) {
203 switch (i) {
204 case 0:
205 imx_iomux_v3_setup_multiple_pads(
206 usdhc1_pads, ARRAY_SIZE(usdhc1_pads));
207 gpio_direction_input(USDHC1_CD_GPIO);
208 usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK);
209 break;
210 case 1:
211 imx_iomux_v3_setup_multiple_pads(
212 usdhc2_pads, ARRAY_SIZE(usdhc2_pads));
213 gpio_direction_input(USDHC2_CD_GPIO);
214 usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
215 break;
216 case 2:
217 imx_iomux_v3_setup_multiple_pads(
218 usdhc3_pads, ARRAY_SIZE(usdhc3_pads));
219 gpio_direction_input(USDHC3_CD_GPIO);
220 usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
221 break;
222 default:
223 printf("Warning: you configured more USDHC controllers"
224 "(%d) than supported by the board\n", i + 1);
225 return -EINVAL;
226 }
227
228 ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);
229 if (ret) {
230 printf("Warning: failed to initialize "
231 "mmc dev %d\n", i);
232 return ret;
233 }
234 }
235
236 return 0;
237}
238
239#ifdef CONFIG_SYS_I2C_MXC
240#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
241
242struct i2c_pads_info i2c_pad_info1 = {
243 .sda = {
244 .i2c_mode = MX6_PAD_I2C1_SDA__I2C1_SDA | PC,
245 .gpio_mode = MX6_PAD_I2C1_SDA__GPIO_3_13 | PC,
246 .gp = IMX_GPIO_NR(3, 13),
247 },
248 .scl = {
249 .i2c_mode = MX6_PAD_I2C1_SCL__I2C1_SCL | PC,
250 .gpio_mode = MX6_PAD_I2C1_SCL__GPIO_3_12 | PC,
251 .gp = IMX_GPIO_NR(3, 12),
252 },
253};
254
255int power_init_board(void)
256{
257 struct pmic *p;
258
259 p = pfuze_common_init(I2C_PMIC);
260 if (!p)
261 return -ENODEV;
262
263 return pfuze_mode_init(p, APS_PFM);
264}
265#endif
266
267#ifdef CONFIG_FEC_MXC
268int board_eth_init(bd_t *bis)
269{
270 setup_iomux_fec();
271
272 return cpu_eth_init(bis);
273}
274
275static int setup_fec(void)
276{
277 struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
278
279
280 clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0);
281
282 return enable_fec_anatop_clock(ENET_50MHZ);
283}
284#endif
285
286#ifdef CONFIG_USB_EHCI_MX6
287#define USB_OTHERREGS_OFFSET 0x800
288#define UCTRL_PWR_POL (1 << 9)
289
290static iomux_v3_cfg_t const usb_otg_pads[] = {
291
292 MX6_PAD_KEY_COL4__USB_USBOTG1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL),
293 MX6_PAD_EPDC_PWRCOM__ANATOP_USBOTG1_ID | MUX_PAD_CTRL(OTGID_PAD_CTRL),
294
295 MX6_PAD_KEY_COL5__USB_USBOTG2_PWR | MUX_PAD_CTRL(NO_PAD_CTRL)
296};
297
298static void setup_usb(void)
299{
300 imx_iomux_v3_setup_multiple_pads(usb_otg_pads,
301 ARRAY_SIZE(usb_otg_pads));
302}
303
304int board_usb_phy_mode(int port)
305{
306 if (port == 1)
307 return USB_INIT_HOST;
308 else
309 return usb_phy_mode(port);
310}
311
312int board_ehci_hcd_init(int port)
313{
314 u32 *usbnc_usb_ctrl;
315
316 if (port > 1)
317 return -EINVAL;
318
319 usbnc_usb_ctrl = (u32 *)(USB_BASE_ADDR + USB_OTHERREGS_OFFSET +
320 port * 4);
321
322
323 setbits_le32(usbnc_usb_ctrl, UCTRL_PWR_POL);
324
325 return 0;
326}
327#endif
328
329int board_early_init_f(void)
330{
331 setup_iomux_uart();
332#ifdef CONFIG_MXC_SPI
333 setup_spi();
334#endif
335 return 0;
336}
337
338int board_init(void)
339{
340
341 gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
342
343#ifdef CONFIG_SYS_I2C_MXC
344 setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1);
345#endif
346
347#ifdef CONFIG_FEC_MXC
348 setup_fec();
349#endif
350
351#ifdef CONFIG_USB_EHCI_MX6
352 setup_usb();
353#endif
354
355 return 0;
356}
357
358int checkboard(void)
359{
360 puts("Board: MX6SLEVK\n");
361
362 return 0;
363}
364
