LXR uboot/board/ti/panda/panda.c

   1/*
   2 * (C) Copyright 2010
   3 * Texas Instruments Incorporated, <www.ti.com>
   4 * Steve Sakoman  <steve@sakoman.com>
   5 *
   6 * SPDX-License-Identifier:     GPL-2.0+
   7 */
   8#include <common.h>
   9#include <asm/arch/sys_proto.h>
  10#include <asm/arch/mmc_host_def.h>
  11#include <asm/arch/clock.h>
  12#include <asm/arch/gpio.h>
  13#include <asm/gpio.h>
  14
  15#include "panda_mux_data.h"
  16
  17#ifdef CONFIG_USB_EHCI
  18#include <usb.h>
  19#include <asm/arch/ehci.h>
  20#include <asm/ehci-omap.h>
  21#endif
  22
  23#define PANDA_ULPI_PHY_TYPE_GPIO       182
  24#define PANDA_BOARD_ID_1_GPIO          101
  25#define PANDA_ES_BOARD_ID_1_GPIO        48
  26#define PANDA_BOARD_ID_2_GPIO          171
  27#define PANDA_ES_BOARD_ID_3_GPIO         3
  28#define PANDA_ES_BOARD_ID_4_GPIO         2
  29
  30DECLARE_GLOBAL_DATA_PTR;
  31
  32const struct omap_sysinfo sysinfo = {
  33        "Board: OMAP4 Panda\n"
  34};
  35
  36struct omap4_scrm_regs *const scrm = (struct omap4_scrm_regs *)0x4a30a000;
  37
  38/**
  39 * @brief board_init
  40 *
  41 * @return 0
  42 */
  43int board_init(void)
  44{
  45        gpmc_init();
  46
  47        gd->bd->bi_arch_number = MACH_TYPE_OMAP4_PANDA;
  48        gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
  49
  50        return 0;
  51}
  52
  53int board_eth_init(bd_t *bis)
  54{
  55        return 0;
  56}
  57
  58/*
  59* Routine: get_board_revision
  60* Description: Detect if we are running on a panda revision A1-A6,
  61*              or an ES panda board. This can be done by reading
  62*              the level of GPIOs and checking the processor revisions.
  63*              This should result in:
  64*                       Panda 4430:
  65*              GPIO171, GPIO101, GPIO182: 0 1 1 => A1-A5
  66*              GPIO171, GPIO101, GPIO182: 1 0 1 => A6
  67*                       Panda ES:
  68*              GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 0 1 1 => B1/B2
  69*              GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 1 1 1 => B3
  70*/
  71int get_board_revision(void)
  72{
  73        int board_id0, board_id1, board_id2;
  74        int board_id3, board_id4;
  75        int board_id;
  76
  77        int processor_rev = omap_revision();
  78
  79        /* Setup the mux for the common board ID pins (gpio 171 and 182) */
  80        writew((IEN | M3), (*ctrl)->control_padconf_core_base + UNIPRO_TX0);
  81        writew((IEN | M3), (*ctrl)->control_padconf_core_base + FREF_CLK2_OUT);
  82
  83        board_id0 = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);
  84        board_id2 = gpio_get_value(PANDA_BOARD_ID_2_GPIO);
  85
  86        if ((processor_rev >= OMAP4460_ES1_0 &&
  87             processor_rev <= OMAP4460_ES1_1)) {
  88                /*
  89                 * Setup the mux for the ES specific board ID pins (gpio 101,
  90                 * 2 and 3.
  91                 */
  92                writew((IEN | M3), (*ctrl)->control_padconf_core_base +
  93                                GPMC_A24);
  94                writew((IEN | M3), (*ctrl)->control_padconf_core_base +
  95                                UNIPRO_RY0);
  96                writew((IEN | M3), (*ctrl)->control_padconf_core_base +
  97                                UNIPRO_RX1);
  98
  99                board_id1 = gpio_get_value(PANDA_ES_BOARD_ID_1_GPIO);
 100                board_id3 = gpio_get_value(PANDA_ES_BOARD_ID_3_GPIO);
 101                board_id4 = gpio_get_value(PANDA_ES_BOARD_ID_4_GPIO);
 102
 103#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 104                setenv("board_name", strcat(CONFIG_SYS_BOARD, "-es"));
 105#endif
 106                board_id = ((board_id4 << 4) | (board_id3 << 3) |
 107                        (board_id2 << 2) | (board_id1 << 1) | (board_id0));
 108        } else {
 109                /* Setup the mux for the Ax specific board ID pins (gpio 101) */
 110                writew((IEN | M3), (*ctrl)->control_padconf_core_base +
 111                                FREF_CLK2_OUT);
 112
 113                board_id1 = gpio_get_value(PANDA_BOARD_ID_1_GPIO);
 114                board_id = ((board_id2 << 2) | (board_id1 << 1) | (board_id0));
 115
 116#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
 117                if ((board_id >= 0x3) && (processor_rev == OMAP4430_ES2_3))
 118                        setenv("board_name", strcat(CONFIG_SYS_BOARD, "-a4"));
 119#endif
 120        }
 121
 122        return board_id;
 123}
 124
 125/**
 126 * is_panda_es_rev_b3() - Detect if we are running on rev B3 of panda board ES
 127 *
 128 *
 129 * Detect if we are running on B3 version of ES panda board,
 130 * This can be done by reading the level of GPIO 171 and checking the
 131 * processor revisions.
 132 * GPIO171: 1 => Panda ES Rev B3
 133 *
 134 * Return : return 1 if Panda ES Rev B3 , else return 0
 135 */
 136u8 is_panda_es_rev_b3(void)
 137{
 138        int processor_rev = omap_revision();
 139        int ret = 0;
 140
 141        if ((processor_rev >= OMAP4460_ES1_0 &&
 142             processor_rev <= OMAP4460_ES1_1)) {
 143
 144                /* Setup the mux for the common board ID pins (gpio 171) */
 145                writew((IEN | M3),
 146                        (*ctrl)->control_padconf_core_base + UNIPRO_TX0);
 147
 148                /* if processor_rev is panda ES and GPIO171 is 1,it is rev b3 */
 149                ret = gpio_get_value(PANDA_BOARD_ID_2_GPIO);
 150        }
 151        return ret;
 152}
 153
 154#ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 155/*
 156 * emif_get_reg_dump() - emif_get_reg_dump strong function
 157 *
 158 * @emif_nr - emif base
 159 * @regs - reg dump of timing values
 160 *
 161 * Strong function to override emif_get_reg_dump weak function in sdram_elpida.c
 162 */
 163void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 164{
 165        u32 omap4_rev = omap_revision();
 166
 167        /* Same devices and geometry on both EMIFs */
 168        if (omap4_rev == OMAP4430_ES1_0)
 169                *regs = &emif_regs_elpida_380_mhz_1cs;
 170        else if (omap4_rev == OMAP4430_ES2_0)
 171                *regs = &emif_regs_elpida_200_mhz_2cs;
 172        else if (omap4_rev == OMAP4430_ES2_3)
 173                *regs = &emif_regs_elpida_400_mhz_1cs;
 174        else if (omap4_rev < OMAP4470_ES1_0) {
 175                if(is_panda_es_rev_b3())
 176                        *regs = &emif_regs_elpida_400_mhz_1cs;
 177                else
 178                        *regs = &emif_regs_elpida_400_mhz_2cs;
 179        }
 180        else
 181                *regs = &emif_regs_elpida_400_mhz_1cs;
 182}
 183
 184void emif_get_dmm_regs(const struct dmm_lisa_map_regs
 185                                                **dmm_lisa_regs)
 186{
 187        u32 omap_rev = omap_revision();
 188
 189        if (omap_rev == OMAP4430_ES1_0)
 190                *dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
 191        else if (omap_rev == OMAP4430_ES2_3)
 192                *dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
 193        else if (omap_rev < OMAP4460_ES1_0)
 194                *dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
 195        else
 196                *dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2;
 197}
 198
 199#endif
 200
 201/**
 202 * @brief misc_init_r - Configure Panda board specific configurations
 203 * such as power configurations, ethernet initialization as phase2 of
 204 * boot sequence
 205 *
 206 * @return 0
 207 */
 208int misc_init_r(void)
 209{
 210        int phy_type;
 211        u32 auxclk, altclksrc;
 212        u32 id[4];
 213
 214        /* EHCI is not supported on ES1.0 */
 215        if (omap_revision() == OMAP4430_ES1_0)
 216                return 0;
 217
 218        get_board_revision();
 219
 220        gpio_direction_input(PANDA_ULPI_PHY_TYPE_GPIO);
 221        phy_type = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);
 222
 223        if (phy_type == 1) {
 224                /* ULPI PHY supplied by auxclk3 derived from sys_clk */
 225                debug("ULPI PHY supplied by auxclk3\n");
 226
 227                auxclk = readl(&scrm->auxclk3);
 228                /* Select sys_clk */
 229                auxclk &= ~AUXCLK_SRCSELECT_MASK;
 230                auxclk |=  AUXCLK_SRCSELECT_SYS_CLK << AUXCLK_SRCSELECT_SHIFT;
 231                /* Set the divisor to 2 */
 232                auxclk &= ~AUXCLK_CLKDIV_MASK;
 233                auxclk |= AUXCLK_CLKDIV_2 << AUXCLK_CLKDIV_SHIFT;
 234                /* Request auxilary clock #3 */
 235                auxclk |= AUXCLK_ENABLE_MASK;
 236
 237                writel(auxclk, &scrm->auxclk3);
 238        } else {
 239                /* ULPI PHY supplied by auxclk1 derived from PER dpll */
 240                debug("ULPI PHY supplied by auxclk1\n");
 241
 242                auxclk = readl(&scrm->auxclk1);
 243                /* Select per DPLL */
 244                auxclk &= ~AUXCLK_SRCSELECT_MASK;
 245                auxclk |=  AUXCLK_SRCSELECT_PER_DPLL << AUXCLK_SRCSELECT_SHIFT;
 246                /* Set the divisor to 16 */
 247                auxclk &= ~AUXCLK_CLKDIV_MASK;
 248                auxclk |= AUXCLK_CLKDIV_16 << AUXCLK_CLKDIV_SHIFT;
 249                /* Request auxilary clock #3 */
 250                auxclk |= AUXCLK_ENABLE_MASK;
 251
 252                writel(auxclk, &scrm->auxclk1);
 253        }
 254
 255        altclksrc = readl(&scrm->altclksrc);
 256
 257        /* Activate alternate system clock supplier */
 258        altclksrc &= ~ALTCLKSRC_MODE_MASK;
 259        altclksrc |= ALTCLKSRC_MODE_ACTIVE;
 260
 261        /* enable clocks */
 262        altclksrc |= ALTCLKSRC_ENABLE_INT_MASK | ALTCLKSRC_ENABLE_EXT_MASK;
 263
 264        writel(altclksrc, &scrm->altclksrc);
 265
 266        id[0] = readl(STD_FUSE_DIE_ID_0);
 267        id[1] = readl(STD_FUSE_DIE_ID_1);
 268        id[2] = readl(STD_FUSE_DIE_ID_2);
 269        id[3] = readl(STD_FUSE_DIE_ID_3);
 270        usb_fake_mac_from_die_id(id);
 271
 272        return 0;
 273}
 274
 275void set_muxconf_regs_essential(void)
 276{
 277        do_set_mux((*ctrl)->control_padconf_core_base,
 278                   core_padconf_array_essential,
 279                   sizeof(core_padconf_array_essential) /
 280                   sizeof(struct pad_conf_entry));
 281
 282        do_set_mux((*ctrl)->control_padconf_wkup_base,
 283                   wkup_padconf_array_essential,
 284                   sizeof(wkup_padconf_array_essential) /
 285                   sizeof(struct pad_conf_entry));
 286
 287        if (omap_revision() >= OMAP4460_ES1_0)
 288                do_set_mux((*ctrl)->control_padconf_wkup_base,
 289                           wkup_padconf_array_essential_4460,
 290                           sizeof(wkup_padconf_array_essential_4460) /
 291                           sizeof(struct pad_conf_entry));
 292}
 293
 294#if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_GENERIC_MMC)
 295int board_mmc_init(bd_t *bis)
 296{
 297        return omap_mmc_init(0, 0, 0, -1, -1);
 298}
 299#endif
 300
 301#ifdef CONFIG_USB_EHCI
 302
 303static struct omap_usbhs_board_data usbhs_bdata = {
 304        .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
 305        .port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
 306        .port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
 307};
 308
 309int ehci_hcd_init(int index, enum usb_init_type init,
 310                struct ehci_hccr **hccr, struct ehci_hcor **hcor)
 311{
 312        int ret;
 313        unsigned int utmi_clk;
 314
 315        /* Now we can enable our port clocks */
 316        utmi_clk = readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL);
 317        utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK;
 318        setbits_le32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, utmi_clk);
 319
 320        ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
 321        if (ret < 0)
 322                return ret;
 323
 324        return 0;
 325}
 326
 327int ehci_hcd_stop(int index)
 328{
 329        return omap_ehci_hcd_stop();
 330}
 331#endif
 332
 333/*
 334 * get_board_rev() - get board revision
 335 */
 336u32 get_board_rev(void)
 337{
 338        return 0x20;
 339}
 340